Chapter 4 FPM Receiver Setup (PanelLink) (for PCA-6654 only)
59
6.
Set S2 according to the following table:
Table 4-30: LCD clock configuration select (S2)
Frequency/data latch edge/mode
Pin 1 Pin 2# Pin 3
Pin 4
divided by 1/negative/free running
ON
X
ON
ON
divided by 1/positive/free running
ON
X
OFF
ON
# Termination resistor range selection:
ON:
55 ~ 70
Ω
OFF: 40 ~ 57
Ω
7.
Set J5 as follows:
Table 4-31: LCD bias voltage select (J5)
V
EE
8.
Set J8 as follows:
Table 4-32: LCD signal level select (J8)
* 5 V
3.3 V
* default setting
9.
Set J13 as follows:
Table 4-33: LCD bias voltage setting (J13)
+V
EE
* -V
EE
* default setting
1
1
1
1
1
Содержание PCA-6654
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