Advantech iDAQ-900 Series, Руководство пользователя

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23 iDAQ-900 User Manual
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Sigma-Delta ADC Analog Input Module
Unlike the successive-approximation register (SAR) ADC, which performs one con -
version for each convert clock, the sigma-delta ADC requires a continuous high-fre -
quency oversample clock to perform the conversion. Therefore, this kind of modules
cannot accept the sample clock from the programmable clock divider output of the
chassis, programmable function pins, or signal of other slots as other types of analog
input modules do.
The output data rate of a sigma-delta ADC analog input module is usually limited to
several choices, such as
where N = 1, 2, 4, 8, … etc.
Before starting acquisition, a synchronization pulse will be sent to each sigma-delta
ADC analog input modules to reset the ADCs at the same time. This synchronization
pulse ensures that all sigma-delta ADCs will provide output data at the same time.
Due to the internal digital filter operation, the sigma-delta ADC module exhibits a
fixed “input signal to output data” delay which is also called “group delay” compared
to other types of analog input modules as shown in Figure 3.12. Refer to the specifi -
cations of the corresponding iDAQ module for the delay value.
Figure 3.12 Group delay of the sigma-delta ADC analog input module
The sigma-delta ADC module can generate a data ready timing signal. This signal
can be routed to other non-sigma-delta ADC type modules as their sample clock.