Advantech FWA-1320, Руководство пользователя

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25 FWA-1320 User Manual
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Most of the SMBus devices are only accessed by BIOS at system start up to deter-
mine and set system configuration. Tampering with these devices may lead to system
instability and malfunction.
Information on the hardware monitor and how to access it is provided in section
2.4.9.
Information reg. the FRU EEPROM can be found in section 2.4.9.1.
5. Interrupt Controllers
The PCH contains two cascaded, legacy 8259 interrupt controllers as well as an IO
Advanced APIC. Legacy Interrupts can also be generated via the LPC Bus using the
Serial IRQ mechanism.
The PCH interrupt controllers forward the interrupt requests to the local APIC inte-
grated with the CPU either as out of band INT# requests or MSI/MSI-X in band mes-
sages. For more details on the iA interrupt architecture, please refer to
documentation available from intel.
2.4.4.4 QuickAssist Accelerator
QuickAssist is used by applications running on the IA cores to accelerate and offload
processing. The integrated QuickAssist accelerator appears to software as a PCIe
endpoint and is used as a look-aside coprocessor. It supports the features below:

Symmetric Cryptographic Functions
– Cipher Operations
– Hash/Authenticate Operation
– Cipher-Hash Combined Operation
– Key Derivation Operation

Public Key Functions
– RSA Operation
– Diffie-Helman Operation
– Digital Signature Standard Operation
– Key Derivation Operation
– Elliptic Curve Cryptography: ECDSA* and ECDH*
For more information, please refer to documentation available from intel.
2.4.4.5 Random Number Generator
The ATOM C2000 processor introduces a software visible digital random number
generation mechanism supported by a high-quality entropy source. This capability is
available to programmers through the new RDRAND instruction. The resulting ran-
dom number generation capability complies with existing industry standards (ANSI
X9.82 and NIST SP 800-90). The instruction is described as RDRAND—Read Ran-
dom Number in Volume 2 of the Intel? 64 and IA-32 Architectures Software Devel-
oper’s Manual available from intel.
0 0xA2/A3 DIMM A1 SPD SPD EEPROM
0 0xAC/AD 24C02 System FRU EEPROM
0 0xAE/AF 24C02 (reserved)
Reserved for FRU EEPROM
on PCIe expansion card
0 0xD2/D3 CK420BQ Clock generator
Table 2.14: SMBus Devices