Advantech EVA-X4300, Руководство пользователя

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21 EVA-X4300 System Design Guide
Chapter 2
Layout
Guide
7. Avoid running PCI clocks in parallel with other signals for a long distance, for
interference and coupling.
8. The user may need to drive two or more source-terminated clock lines with sin-
gle output. However, the following condition must be achieved:
i. The clock traces length must be as equal as possible, to guarantee the arriv-
ing time of the reflected pulses.
ii. The loads must be balanced, to guarantee the same shape of the reflected
pulses.
iii. The termination value must be calculated according to:
R
t
= Z
0
– R
s
* N
R
t
= termination resistor, Ω
R
s
= output impedance of the driver
Z
0
= line impedance
N = number of lines
2.10 USB 2.0
1. Route the Hi-Speed USB differential pairs over continuous ground or
power planes. Avoid crossing anti-etch areas and any breaks in the inter-
nal planes (plane splits).
2. Avoid placing a series of vias near the DP and DM lines, as these will create
“break areas” in the ground plane below.
3. Avoid routing the USB differential pairs near I/O connectors, signal headers,
crystals/ oscillators, magnetic and power connectors.
4. Maintain parallelism between USB differential signals, with the trace spacing
needed to achieve
90 Ω differential impedance .
5. We recommend the trace Width/ Spacing/ Isolation of USB differential pairs to
be 8 mil/ 8 mil/ >20 mil . And the mismatch of the differential pairs should be
less than ±70 mil . These values may vary depending on the actual PCB
parameters.
6. The maximum trace length of USB differential pairs should be less than 2” .