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EVA-X4300 System Design Guide

10

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AVDD33_0

DP3

DP2

AVDD33_1 RTC_Xin

AVDD3

XOUT_14.

318

POWER_

GOOD

CLK25MO

UT

DCD2_/

PWM0CLK

CTS2_/

PWM1GAT

E

DSR2_/

PWM0GAT

E

NC

26

AVSSPLL0

DM3

DM2

AVSSPLL1 RTC_Xout

AVSS3

XIN_14.31

8

MTBF

CLK24MO

ut

DTR2_/

PWM2OU

T

RTS2_/

PWM1OU

T

TXD_EN2/

PWM2GAT

E

SIN2/

PWM2CLK

25

REXT0

AVDD1

AVSS2

REXT1

AVDDPLL

1

SERIRQ Vss_pll_1 Vdd_pll_1 Vdd_pll_0 Vss_pll_0

RI2_/

PWM1CLK

SOUT2/

PWM0OU

T

DCD1_/

GPIO_40

24

AVSS1

AVDD2

LAD0

LAD1

LAD2

LAD3

SPEAKER Vdd_core

Vss_io

Vdd_io

DTR1_/

GPIO_45

CTS1_/

GPIO_47

DSR1_/

GPIO_46

23

RTC_RD_

GPIO_36

RTC_IRQ8
_/GPIO_34

RTC_PS

SYSFAILO

ut_

Ext_Switch

_fail_

E_SPI_CL

K/

GPIOP_31

E_SPI_DI/

GPIOP_33

Vdd_core

Vss_io

Vdd_io

RI1_/

GPIO_43

SOUT1/

GPIO_41

RTS1_/

GPIO_42

22

VBat

VBatGnd

RTC_WR_

GPIO_35

ExtSysFailI

n_

EXT_GPC

S_

E_SPI_CS

/

GPIOP_30

E_SPI_DO

/

GPIOP_32

Vdd_core

Vss_io

Vdd_io

TXD_EN1

SIN1/

GPIO_44

GPIO_P2_

1/SA25

21

GPIO_P2_

7/SA31

GPIO_P2_

6/SA30

Vss_io

GPIO_P2_

5/SA29

GPIO_P2_

4/SA28

GPIO_P2_

2/SA26

20

GPIO_P1_

7

GPIO_P2_

0/SA24

GPIO_P1_

6

GPIO_P1_

5

GPIO_P1_

4

GPIO_P1_

0

19

Vss_io

Vss_io

Vss_core LFRAME_

LDRQ_

GPIO_P0_

7

GPIO_P1_

3

GPIO_P1_

2

GPIO_P2_

3/SA27

GPIO_P0_

5

GPIO_P0_

3

18

Vss_io

Vss_io

Vss_core

Vss_io

Vss_io

GPIO_P0_

6

GPIO_P1_

1

GPIO_P0_

1

GPIO_P0_

0

GPIO_P0_

4

GPIO_P0_

2

17

Vdd_io

Vss_io

Vss_core Vss_core

KBDATA /

A20GATE_

SD3

IOR_

GPCS0_

GPCS1_

SD15

SD14

16

Vdd_io

Vss_io

Vss_io

Vss_core MSDATA

LA20

LA18

LA23

LA19

DRQ7

SD12

15

VCC3V

Vdd_io

Vss_io

Vss_core

MSCLK

SD4

IRQ9

SD2

SD6

LA21

SD11

14

VCC3V

Vdd_io

Vss_io

Vss_core

KBCLK_K

BRST_

IOCHCK_

SA2

SBHE_

LA22

SA5

DACK_2

13

VCC3V

Vss_io

Vdd_core Vss_core Vss_core

SA3

DRQ0

Vss_core

SD8

MEMW_

SA1

12

VCC3V

Vss_io

Vdd_core Vss_core Vss_core

DRQ5

SA4

Vss_core DACK_6

SD10

DRQ6

11

VCC3V

Vdd_io

Vss_io

Vdd_core Vdd_core

SMEMR_ DACK_5 Vss_core

SD13

SD9

SYSCLK

10

VCCK

Vdd_io

Vss_io

Vss_io

Vss_io

SA19

SA17

DRQ2

DACK_0

LA17

MEMR_

9

SMEMW_

AEN

IRQ12

0WS_

IOCHRDY

_

OSC14M

8

SD0

SA10

SA8

IRQ5

IRQ7

DACK_7

7

CTS4_/

SIOW_

DCD4_/

SA2

DSR4_/

SCS1_

RTS4_/

SINT

DTR4_/

SA0

Vss_io

SD7

Vdd_io

Vss_core Vdd_core

SA7

IRQ10

REFRESH

_

6

PDD12

PDD2

PDD1

PDD11

RI4/SA1

Vss_io

DRQ3

Vdd_io

Vss_core Vdd_core

SA18

SA9

TC

5

PDD10

PDD5

PDD6

PDD7

Vss_core

Vdd_io

SD5

Vdd_io

Vss_core Vdd_core

DRQ1

BALE

IRQ15

4

PIORDY

PIOW_

PDD0

PDD8

Vdd_io

Vdd_io

DACK_3

SA16

DACK_1

SA0

SA11

IOCS16_

IRQ11

3

PA1

PA0

PCS0_

PDD4

PDD15

PDD14

IOW_

SA12

SA14

SA6

SA13

IRQ3

IRQ14

2

PDD13

PDRQ

PDACK_ PCBLID_

PIOR_

PCS1_

SD1

SA15

RSET_DR

V

IRQ6

IRQ4

MEMCS16

_

NC

1

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

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Содержание EVA-X4300

Страница 1: ...User Manual EVA X4300 System Design Guide ...

Страница 2: ...tech is believed to be accurate and reliable However Advantech does not assure any liability arising out of the application or use of this information nor the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Copyright 2008 Advantech Co Ltd All rights reserved Part No 2006X43020 Edition 1 Printed in Tai...

Страница 3: ...ine 4 2 2 Package Outline 6 2 3 Signal Arrangement 8 2 4 EVA X4300 Power Requirement 11 2 5 General Layout Rule 11 2 6 Crystal External Oscillator 15 2 7 DDR2 Interface 16 2 8 Switching Power 19 2 9 PCI Interface 20 2 10 USB 2 0 21 2 11 IDE 23 2 12 LPC Interface 24 2 13 10 100 LAN 25 Appendix A References 29 A 1 References 30 ...

Страница 4: ...EVA X4300 System Design Guide iv ...

Страница 5: ...Chapter 1 1 Overview ...

Страница 6: ...n IDE controller and 256 KB flash within a single 581 pin BGA package to form a an SoC System on Chip processor The EVA X4300 integrates comprehensive features and rich I O flexibility within a single System on Chip to reduce board design complexity and shorten product development schedules Taking advantage of ultra low power consumption the EVA X4300 is able to operate in a wide range of temperat...

Страница 7: ...Chapter 2 2 Layout Guide ...

Страница 8: ...pitch is 1 mm 40 mil There are 6 rows of balls arranged along the edge of the package For 6 layer Ball pad diameter 24 mil Traces width spacing for Signals 5 5 5 mil Trace width for Power and Ground 20 mils Vias PAD Drill diameter for all Signals 14 8 mil Via to via spacing center to center 40 mil Via to pad spacing center to center 30 mil ...

Страница 9: ... Power and Ground 20 mils Vias PAD Drill diameter for all Signals 22 12 mil Via to via spacing center to center 40 mil Via to pad spacing center to center 30 mil Note All the Vias must be covered by solder mask To minimize inductance power vias should be as large as possible and take good care of the inadvertently cut of the ground and power planes ...

Страница 10: ...EVA X4300 System Design Guide 6 2 2 Package Outline ...

Страница 11: ...7 EVA X4300 System Design Guide Chapter 2 Layout Guide ...

Страница 12: ...VA X4300 System Design Guide 8 2 3 Signal Arrangement Top View 26 25 24 23 22 22 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Pin 1 Corner ...

Страница 13: ...R3 15 MD2 MD7 MD11 MD12 MD8 GND_R3 VCC3V VCC3V VCC3V VCC3V GND_R3 14 MD5 DQM0 MD13 DQS0 MD10 VCCK VCCK VCCK VCCK VCCK GND_R3 13 MD6 CS_1 WE_ RAS_ CS_0 VCCK GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 12 MA10 MA6 BA2 BA0 CAS_ BA1 GNDK GNDK GNDK GND_R3 GND_R3 11 MA1 MA5 MA7 MA9 MA11 MA13 GNDK GNDK GNDK GNDK GND_R3 10 MA0 MA3 MA4 VDLL0 GNDDLL0 MA12 GNDK GNDK GNDK GNDK GND_R3 9 SDRAM CLKN SDRAM CLKP MA2 VDLL1 ...

Страница 14: ...PIO_P0_ 5 GPIO_P0_ 3 18 Vss_io Vss_io Vss_core Vss_io Vss_io GPIO_P0_ 6 GPIO_P1_ 1 GPIO_P0_ 1 GPIO_P0_ 0 GPIO_P0_ 4 GPIO_P0_ 2 17 Vdd_io Vss_io Vss_core Vss_core KBDATA A20GATE_ SD3 IOR_ GPCS0_ GPCS1_ SD15 SD14 16 Vdd_io Vss_io Vss_io Vss_core MSDATA LA20 LA18 LA23 LA19 DRQ7 SD12 15 VCC3V Vdd_io Vss_io Vss_core MSCLK SD4 IRQ9 SD2 SD6 LA21 SD11 14 VCC3V Vdd_io Vss_io Vss_core KBCLK_K BRST_ IOCHCK_ ...

Страница 15: ...ock generation circuitry 6 The voltage rating of the bulk capacitors should be 50 higher than the actual voltage level to prevent self destruction and or voltage surge 7 For decoupling of DDR2 interface please check the DDR2 section for more details 8 In digital circuits conductors may be treated as transmission lines if the propa gation time Tdelay is equal to or greater than the pulse transition...

Страница 16: ... the signal plane above a solid ground plane on a multi layer board 13 If clock high speed signals must make a layer jump route ground trace adja cent to the signals and connect both ends of the ground trace to the GND plane to form a RF return path of the signals 14 The split power planes may cause serious EMI and signal integrity problems for high speed signals which run adjacent to the power pl...

Страница 17: ...be isolated from the digital ground and power planes A clean or quiet ground must be located at the point where interconnects leave the system Connect Bridge those grounds with only one connection Only those signals required for operation or interconnect can run into the isolated area ...

Страница 18: ...tors should connect to the same supply VCCO of DRAM interface That is For detail of power on straps function please refer to the EVA X4300 data sheet 22 Do follow the power on sequence to prevent excessive current from the power supplies during power up and power down periods Power up core supply VDD_CORE and then power up the I O supply DVDD Power down I O supply DVDD and then power down the core...

Страница 19: ...of the crystal to EVA X4300 as SHORT as possible When use external crystal with EVA X4300 internal oscillation circuitry to work as clock oscillator be sure to put all the related components close to EVA X4300 chip The ground area under the crystal circuitry should be physically insolated from system ground plane with only a small bridge between them for signals crossing This isolation prevents no...

Страница 20: ...A 1 12989 16 MA 2 8745 03 MA 3 10321 07 MA 4 10173 85 MA 5 11728 8 MA 6 12466 29 MA 7 11480 64 MA 8 7638 44 MA 9 10753 84 MA 10 13659 62 MA 11 9367 04 MA 12 7999 4 MA 13 8948 06 MD 0 12939 2 MD 1 12379 26 MD 2 12218 38 MD 3 12868 28 MD 4 13327 88 MD 5 11731 55 MD 6 11817 28 MD 7 11681 94 MD 8 11494 07 MD 9 10379 54 MD 10 10577 86 MD 11 11902 14 MD 12 11610 42 MD 13 10048 32 MD 14 10981 68 MD 15 12...

Страница 21: ...e DDR2 region 9 All signals avoid crossing over an unrelated plane or different power plane Six or more layers of PCB could eliminate these problems by routing DDR2 signals in the layer that is adjacent to the ground plane s 10 Rout traces with minimal layer transitions and minimize the total number of turns and vias 11 Decoupling capacitors are critical to the reliable operation of the DDR2 inter...

Страница 22: ... resistors can be placed close to the DDR2 devices 18 The decoupling capacitors for VREF are intended to reduce AC noise Place one each at the divider and every VREF input of the DDR2 s 19 Recommended Terminations for DDR2 interface Signal Impedance Ω Value Ω Note Clock Differential 90 33 Near EVA X4300 DQS Near DDR2 A 0 13 BA 0 2 Controls 60 Near EVA X4300 DQM DQ 0 15 Near DDR2 MD 0 15 Near EVA X...

Страница 23: ...rent power plane c Route traces with minimal layer transitions and minimize the total number of turns vias 2 8 Switching Power 1 Please check section 2 3 and DDR2 data sheet for the detailed power require ments of the DDR2 system 2 In a step down switching regulator the input bypass capacitor the main power switch and the freewheeling diode carry discontinuous currents with high dt di For jitter f...

Страница 24: ...nterface 1 We highly recommend reserve terminations for ALL PCI signals It is much easier to remove terminations than adding them after the PCB has been found to fail EMI 2 The trace length for all PCI signals must be limited to 7 inches 3 The trace length for PCI Clocks must be short for on board PCI devices to mini mize the clock skew 4 The PCI clock traces should be parallel to their reference ...

Страница 25: ...nes 2 10 USB 2 0 1 Route the Hi Speed USB differential pairs over continuous ground or power planes Avoid crossing anti etch areas and any breaks in the inter nal planes plane splits 2 Avoid placing a series of vias near the DP and DM lines as these will create break areas in the ground plane below 3 Avoid routing the USB differential pairs near I O connectors signal headers crystals oscillators m...

Страница 26: ...REXT0 1 to keep from interference and coupling 12 Provide a good path from the USB connector shell to the chassis ground 13 Maintain the maximum possible distance between Hi Speed USB differential pairs high speed or lows peed clock and non periodic signals The minimum recommended distances are as follows 20 mils between the DP and DM traces and low speed non periodic signal traces 50 mils between...

Страница 27: ... be serial terminated Place the termination resistors for A 0 2 CS 0 1 IOR IOW and DACK near EVA X4300 Place the termina tion resistors for D 0 15 DRQ IORDY and IRQ near IDE connector 3 The termination value should be optimized to compensate for transceiver and trace impedance to match the characteristic cable impedance 4 The 28th pin of IDE connectors CSEL should be pulled low 5 Signals in the sa...

Страница 28: ... LPC interface is to replace ISA interface serving as a bus interface between the system processor and peripherals e g LPC super I O chip Many of the signals are the same as signals found on the PCI interface Data transfer on the LPC bus is serialized over a 4 bit bus Route the LPC signals with the PCI design rule ...

Страница 29: ...n Guide 4 Keep the distance between the EVA X4300 and the RJ 45 connector short under 4 5 Route the differential traces TX RX TD RD for 100 Ω differential impedance Parameters Specification Note Tx Rx Turns Ratio 1CT 1 CT 1CT 1CT Inductance μH 350 350 Capacitance pF 15 15 DC Resistance Ω 0 9 0 9 Manufacturer Part Number Note Mingtek HN16005CG ...

Страница 30: ...h is isolated from the ground plane of the input side of transformer and EVA X4300 Connect this quiet ground plane to system ground with only one connection bridge Do NOT run any signal into this iso lated area 14 The moat to isolate the quiet ground should be at least 100 mil 15 Avoid laying power and ground planes underneath the magnetic to enhance EMI 16 Provide a good path from the RJ 45 conne...

Страница 31: ...27 EVA X4300 System Design Guide Chapter 2 Layout Guide 21 Avoid over damping which affects LAN stability It is recommend to place 51 ohm and 22 pF from PCI AD0 AD3 ...

Страница 32: ...EVA X4300 System Design Guide 28 ...

Страница 33: ...Appendix A A References ...

Страница 34: ...PCI Local Bus Specification rev 2 2 3 EMC and the Printed Circuit Board Mark I Montrose 4 High speed Digital Design Howard W Johnson PH D 5 Noise reduction Techniques in the Electronic System Henry W Ott 6 Printed Circuit Board design Techniques for EMC Compliance Mark I Mon trose ...

Страница 35: ...31 EVA X4300 System Design Guide Appendix A References ...

Страница 36: ...ations are subject to change without notice No part of this publication may be reproduced in any form or by any means electronic photocopying recording or otherwise without prior written permis sion of the publisher All brand and product names are trademarks or registered trademarks of their respective companies Advantech Co Ltd 2008 ...

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