Advantech EVA-X4300, Руководство пользователя

Страница: 15 / 36

11 EVA-X4300 System Design Guide
Chapter 2
Layout
Guide
2.4 EVA-X4300 Power Requirement
2.5 General Layout Rule
1. Keep all traces as SHORT as possible.
2. Decoupling is to remove the RF energy injected into the power distribution net-
work from high-speed switching devices.
3. Bypassing is to divert unwanted common-mode RF noise from components or
cables coupling from one area to another.
4. Place 0.01 µF~0.1 µF decoupling capacitors across each pair of VCC and GND
pins. Use the shortest and thickest trace between decoupling capacitor and the
VCC/GND pins.
5. Bulk capacitors ensure that a sufficient amount of DC voltage and current is
available for digital components. At least one bulk capacitor should be located:
! Every VLSI device
! Power connector(s)
! Daughter card slots
! Furthest location from the power connector
! Clock generation circuitry
6. The voltage rating of the bulk capacitors should be 50% higher than the actual
voltage level to prevent self-destruction and/ or voltage surge.
7. For decoupling of DDR2 interface, please check the DDR2 section for more
details.
8. In digital circuits, conductors may be treated as transmission lines if the propa-
gation time (T
delay
) is equal to or greater than the pulse transition time (T
rise
or
T
fall
).
9. The propagation speed on typical PCB is about 170 pS/inch (50
Ω
Stripline),
150pS/inch (50
Ω
Microstrip).
10. There are 4 properties affect the performance of the transmission line:
! Impedance: reflection/ distortion
! Time delay
!
High-Frequency Loss: limit signal bandwidth and transmission distance
! Crosstalk: coupling
DC Volt Tolerance Ripple & Noise Max. Current
3.3V for VCCP ± 0.30 V < 100 mV 185 mA
3.3V for VCCO
1.8V for VCCO ± 0.15 V
± 0.09 V
< 50 mA < 245 mA
DC Volt Min. Volt Max. Volt Ripple & Noise Max. Current
1.3V for VCCK 1.30 V 1.40 V < 50 mA 240 mA
Note! CPU clock 300 MHz, DDR2 clock 133 MHz and PCI clock 33 MHz