Advantech ARK-1388V, Руководство пользователя, Страница: 42 / 109

ARK-1388V User Manual 32
3.2.4 Advanced Chipset Features
! DRAM Timing Selectable [By SPD]
This item allows the user to set the optimal timings for items 2 through 5, sys-
tem default setting of "By SPD" to follow the SPD information and ensure the
system running in stable and optimal performance.
! CAS Latency Time [Auto]
This item allows the user to set the timing delay in clock cycles before SDRAM
start a read command after receiving it.
! DRAM RAS# to CAS# Delay [Auto]
This item allows the user to set the timing of the transition from RAS (row
address strobe) to CAS (column address strobe) as both rows and column are
separately addressed shortly after DRAM is refreshed.
! DRAM RAS# Precharge [Auto]
This item allows the user to set the DRAM RAS# precharge timing, system
default is setting to "Auto" to reference the data from SPD ROM.
! Precharge delay (tRAS) [Auto]
This item allows the user to adjust memory precharge time
! System Memory Frequency [Auto]
This item allows the user to adjust memory frequency to improvement perfor-
mance.
Note! The "Advanced Chipset Features" screen controls the configuration of
the board's chipset register settings and performance tuning - the
options on this screen may vary depending on the chipset type. It is
strongly recommended that only technical users make changes to the
default settings.