ADLINK Technology USBDAQ-9100MS, Руководство пользователя

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Operation Theorem
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31
The following diagram shows the timing diagram.
Clock
WR
Gate
Output
4 3 2 1 0
n = 4
Mode 5 : Hardware Triggered Strobe(Retriggerable)
In this mode is similar to Software Trigger mode except that the gate input
is used as a trigger to start counting.
The following diagram shows the timing diagram.
Clock
Gate
Output
4 3 2 1 0
n = 4
Input/Ouput Diagram
The 8254 input/output pins are TTL-compatible without isolation. So
please be aware about the signal connection.