ADLINK Technology USBDAQ-9100MS, Руководство пользователя

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Operation Theorem
The following diagram shows the timing diagram.
Clock
Gate
Output
4 3 2 1 0
(n = 4)
Mode 2 : Rate Generator
In this mode, the output goes low for one period of the clock input. The
value fill in the counter indicates the period from one output pulse to the
next.
The following diagram shows the timing diagram.
Clock
Gate
Output
4 3 2 1 0 (4) 3 2 1 0 (4)
(n = 4)
Mode 3 : Square Wave Mode
In this mode, the output stays high for one half of the
count
clock pulses
and stays low for the other half.
The following diagram shows the timing diagram.
Clock
Gate
Output (n = 4)
4 2 4 2 4 2 4 2 4 2 4 2
Output (n = 5)
5 4 2 5 2 5 4 2 5 2 5 4
Mode 4 : Software Triggered Strobe
In this mode, the output is initially high, and the counter begins to count
down while the gate input is high. On terminal count, the output goes
low for one clock pulse, and goes high again.