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16 Register Format
3.6 COS Latch Register
When COS occurs, the COS Latch Register also latches DI data,
until the interrupt request is cleared, at which point the COS Latch
register is automatically cleared. The COS function frees the CPU
from the task of polling all input channels, increasing I/O perfor-
mance.
Address: BASE + 0x06
Attribute: Read
CL x: COS latch register of DI channel x, x = 0 ~ 15
1: digital input voltage is in high level
0: digital input voltage is in low level
3.7 Interrupt Control Register
In a first interrupt mode, COS interrupt function is enabled to mon-
itor the enabled input channel’s status whenever the status
changes from 0 to 1 or 1 to 0. In a second mode, digital input
channel 0, channel 1, or both can be selected as interrupt sources.
In this mode, interrupt only asserts when DI status changes from 0
to 1, that is, the rising edge. Because the two modes share the
same interrupt signal in the hardware, both cannot be enabled at
the same time. After processing the interrupt request event, the
interrupt request must be cleared to handle another interrupt
request. To clear the interrupt request, write 1 to the correspond-
ing bit.
7 6 5 4 3 2 1 0
CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0
15 14 13 12 11 10 9 8
CL15 CL14 CL13 CL12 CL11 CL10 CL9 CL8