ADLINK Technology PCIe-7256, Руководство пользователя, Страница: 23 / 40

Register Format 13
PCIe-7256
3 Register Format
The following detailed register format descriptions are helpful for
low-level programming, although it is recommended that users
first fully understand the PCIe interface.
3.1 I/O Address Map
PCIe-7256 registers are all 16 bits wide, accessible only via 16-bit
I/O instruction. Relays and status of isolation input is controlled by
register access. The register map, including descriptions and off-
set addresses relative to the base address, is as follows.
Table 3-1: PCIe-7256 Register Map
3.2 Relay Output Control Register
The 16 latching relays are each controlled by two bits of the con-
trol register. Setting (0,1) indicates the latching relay is in RESET,
under which normal open (NO) signal line is ‘open’ from the com-
mon (COM) line, and the normal close (NC) signal line is con-
nected with the common line. Setting (1,0) indicates the normal
open signal line is now closed, while the NC signal is open.
Note that filling the register with (1,1) can cause uncertain output
status of the relay.
Offset Write Read
0x00h Relay output CH 0 to 7 --
0x02h Relay output CH 8 to 15 Relay output read back CH 0 to 15
0x04h --- Isolated input CH. 0 to 15
0x06h COS setup register COS latch register
0x08h Interrupt control register Interrupt status register