ADLINK Technology NuDAQ PCI-9810, Руководство пользователя

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Registers 21
4.3 ADC Clock Divisor Register
Feeding the ADC source clock to a clock frequency divider
generates the ADC sampling clock. The output of the frequency
divider becomes the sampling clock. The frequency of the ADC
sampling clock is:
Frequency of source clock / ADC clock divisor
Address: BASE + 04h
Attribute: write only
Data Format:
DIV15..0: The AD clock frequency devisor
---: Any value
Bit 7 6 5 4 3 2 1 0
Base + 4 DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
Base + 5 DIV15 DIV14 DIV13 DIV12 DIV11 DIV10 DIV9 DIV8
Base + 6
--- --- --- --- --- --- --- ---
Base + 7 --- --- --- --- --- --- --- ---
Note: The minimum value of this register is 2, and the DIV0
is hardwired to 0.