
Operation Theory
33
Note: * Not available on PCI-7224.
When the IRQ source is set as P1C0 OR P1C3, the IRQ trigger
conditions are summarized in table 4.4.
Because P1/P2C0 and P1/P2C3 are external signals, the user can
utilize the combination of the four signals to generate a proper
IRQ.
INT1
D3 D2 D1 D0 IRQ Source
IRQ Trigger Condition
Disable
X
X
0
0
INT1 disable
--
Mode 1
X
X
0
1
~P1C0
falling edge of P1C0
Mode 2
X
X
1
0
P1C0 OR ~P1C3 (see following)
Mode 3
X
X
1
1
Event Counter
Counter count down to 0
INT2
D3 D2 D1 D0 IRQ Source
IRQ Trigger Condition
Disable
0
0
X
X
INT2 disable
--
Mode 1
0
1
X
X
~P2C0
falling edge of P2C0(*)
Mode 2
1
0
X
X
P2C0 OR ~P2C3 (see following) (*)
Mode 3
1
1
X
X
Timer Output
Timer count down to 0
Table 4-3: ISC register format
P1/2C0 P1/2C3 IRQ Trigger Condition
High
X
PC0=H disable all IRQ
X
Low
PC3=L disable all IRQ
Low
1->0
PC3 falling edge trigger when PC0=L
0->1
High
PC0 rising edge trigger when PC3=H
Table 4-4: IRQ Trigger conditions
Содержание NuDAQ cPCI-7249R
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