
32
Operation
Theory
4.3.3
Note for Dual Interrupts
The PCI controller of PCI-7224/7248/96 can receive two hardware
IRQ sources. However, a PCI controller can generate only one
IRQ to PCI bus, the two IRQ sources must be distinguished by
ISR of the application software if the two IRQ are all used.
The application software can use the “_72xx_Get_Irq_Status”
function to distinguish which interrupt is inserted. After an ISR is
completed, users must check if another IRQ is also asserted, then
clear the current IRQ to allow room for the next IRQ.
The two IRQs are called INT1 and INT2. In PCI-7224/7248/7296,
INT1 comes from P1C0, P1C3 or the event counter interrupt. INT2
comes from P2C0, P2C3 or the timer interrupt. However in PCI-
7224, INT2 only comes from timer interrupt. The sources of INT1
and INT2 are selectable by the Interrupt Source Control (ISC)
Register.
4.3.4
Interrupt Source Control
In ISC register (offset 0x20), there are four bits to control the IRQ
sources of INT1 and INT2.
If the application requires only one IRQ, one of the IRQ sources
can be disabled by software. If no IRQ source is required, both
interrupts can be disabled. However if the user only disables the
IRQ source without changing the initial condition of the PCI con-
troller, the PCI BIOS will still assign a IRQ level to the PCI card
and occupy the PC resource.
It is not recommended to change the initial condition of the PCI
card by the user’s own application software. If the user wishes to
disable the IRQ level, they can use ADLINK’s utility
‘INIT7248.EXE’ or ‘INIT7296.EXE’ to change power on interrupt
setting.
Table 4.3 shows the register format of the ISC (address offset
0x20). This register is write only. The four LSBs are used to control
the source of INT1 and INT2.
Содержание NuDAQ cPCI-7249R
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