7352 Series Digital Multimeter Operation Manual
6.6.5 Status Register Structure
6-48
4. Standard event status register
Allocation in the standard event register is shown in Table 6-5.
Conditions which clear the standard event status register
• When the power is turned on.
• When the *CLS command is executed.
• When the *ESR? command is executed.
Conditions which clear the standard event status enable register
• When the power is turned on. (When the PSC flag is set to 1)
• When the *ESE0 command is executed.
Table 6-5 Standard Event Status Register (ESR)
bit
Name
Description
0
OPC
Operation Complete
ON: This bit is set to 1 when all operations are complete after receiving the *OPC
command.
1
Not used
Always 0
2
Not used
Always 0
3
DDE
Device Dependent
Error
ON: This bit is set to 1 when the error, which depends on the device, occurs.
4
EXE
Execution Error
ON: This bit is set to 1 when the received command cannot be executed.
This bit is set to 1 when the command parameter contains an error.
5
CME
Command Error
ON: This bit is set to 1 when the received command spelling is incorrect.
6
Not used
Always 0
7
PON
Power On
ON: This bit is set to 1 when the power is turned on.
