Active Technologies AT-1212, Руководство пользователя

Страница: 14 / 41

AT-1212 User Guide and Specifications - 14 - www.activetechnologies.it
LabView Interface
Target Side - ReadWriteTablesTest1212.vi
There are two DACs installed on the board that control the two available analog output channels.
The DAC contains two parallel LVDS input ports consisting of 14 differential LVDS signals DB[13:0].
Each data port runs internally at half the speed of the DAC Clock (1.25GHz), so the user needs to
guarantee them the correct data rate.
PORT 1 DATA - CH0
The LabView interface of the CLIP reads data from the look up tables
(Memory1,Memory3,Memory5,Memory7) at IO Module Clock rate (156.25 MHz); the
datadac_in0_ch0/ datadac_in2_ch0/datadac_in4_ch0/datadac_in6_ch0 are internally serialized by 4
to obtain a data rate of 625MS/s.
PORT 2 DATA - CH0
The LabView interface of the CLIP reads data from the look up tables
(Memory2,Memory4,Memory6,Memory8) at IO Module Clock rate (156.25 MHz); the
datadac_in1_ch0/ datadac_in3_ch0/datadac_in5_ch0/datadac_in7_ch0 are internally serialized by 4
to obtain a data rate of 625MS/s.
PORT 1 DATA - CH1
The LabView interface of the CLIP reads data from the look up tables
(Memory9,Memory11,Memory13,Memory15) at IO Module Clock rate (156.25 MHz); the
datadac_in0_ch1/ datadac_in2_ch1/datadac_in4_ch1/datadac_in6_ch1 are internally serialized by 4
to obtain a data rate of 625MS/s.
PORT 2 DATA - CH1
The LabView interface of the CLIP reads data from the look up tables
(Memory10,Memory12,Memory14,Memory16) at IO Module Clock rate (156.25 MHz); the
datadac_in1_ch1/ datadac_in3_ch1/datadac_in5_ch1/datadac_in7_ch1 are internally serialized by 4
to obtain a data rate of 625MS/s.
The Clip provides also access to DDS/Arbitrary mode selection,Clock Selection, Trigger In and Trigger
Out resources, START_CH Generation command and EN_CH0/EN_CH1 to enable/disable channels.
The user has to load each look-up tables with the same waveform and the CLIP reads them updating
the Start/Stop Address and Increment parameters to convey parallel data stream at the converter at
high speeds.