Active Technologies AT-1212, Руководство пользователя

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AT-1212 User Guide and Specifications - 12 - www.activetechnologies.it
trig_in Output Check if the SMA Trigger IN signal is high or
low
trig_out Input Send the Trigger Output to the FAM
clkenable Input Enable/Disable the FPGA DCM clock outputs
clocksel Input Select the clock source for DAC/OSerdes.
The user should set it to false if he needs to
use the TCXO onboard clock or set it to true if
he needs to use the clock coming from the
Timing Board (PXIe backplane).
Clocking Scheme
The DAC clock can be sourced from the internal Clock Generator circuit on the adapter module or
from the outside using the SMA CLK IN (external clock).
The Clock Generator clock can be sourced from the internal TCXO oscillator (25 MHz) or from the PXI
Express backplane clock.
In software, use the
ClockSelection1212.vi to select from the different clock sources.
If the user selects Internal and From Oscillator , the 25 MHz onboard TCXO will provide the clock to
the Clock Generator input. The clock generator generates 1.25GHz, the DAC divides it by 4 and it
provides 312.5 MHz clock to FlexRIO FPGA.
The BUFR and PLL_156M instances divide the 312.5 MHz clock by 2 and it provide the 312.5 MHz and
156.25 MHz clocks to the OSerdes and FlexRIO interface.
If the user selects Internal and From FPGA Clock , the FAM takes the 156.25MHz from the PXI Express
backplane, so the user should provide the clock through DSTARA clock by using the NI timing board.
If the user selects External , the DAC clock (1.25 GHz) has to be provided by outside using the SMA CLK
IN bypassing the clock generator circuit.