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VSBC-6872 series
ACTIS Computer
32
3.15.2 VMEbus Master
The VSBC-6872 is VME Master A32/A24/A16/D32/D16/D8/RMW
The VME master can use two windows to access the VMEbus. They are controlled by the UPM, with the
chip selects CS6 and CS7. All VME Chip Selects take a CPU space of 64 MBytes.
The selection for A16, A24, and A32 modes are made by accessing different offsets in the chip select
memory:
Offset
VME Zone
Size
0x000'0000-0x1ff'ffff
A32
32 MBytes
0x200'0000-0x2ff'ffff
A24
16 MBytes
0x300'0000-0x300'ffff
A16
64 kBytes
Table 14 - VME Master addressing space mapping
For A16 and A24 modes, all VME memory map is directly available.
For A32 mode, the
VMBMA
and
VMBMB
registers define the seven high order bits for A32 VME
addresses. Thus, the VME 32 MBytes windows can be moved in all A32 memory space: 4 GBytes.
Depending on the offset accessed, the AM5 to AM3 are automatically set with the corresponding value to
indicate the address mode used. The AM2 to AM0 bits are user defined in the
VMAMA
and
VMAMB
registers. Setting must be done according to the VMEbus specification.
The selection for D8, D16, and D32 are made dynamically with the software. A byte access generates
automatically a VME D8 access, a word access a D16 access, and a long word access a D32 access.
It is possible to restrict the maximum size of the VME access modifying the Port Size field in the
corresponding Base Register (BR[PS]) of the MPC8270.
D16 and D32 accesses are only allowed on even addresses
The VME Master RMW cycle is controlled by VMBA[RMW]. Please refer to the
VMBA
register description
for correct usage.
It is also possible to lock the VMEbus to get exclusive access of the bus. Please refer to
3.15.4 VMEbus
Requester
for more information.
3.15.3 VMEbus Slave
The VSBC-6872 is slave A24/A16/ D32/D16/D8/RMW.
The board contains an independent slave module. This module doesn't need the local processor
initialized to be active.
From the VMEbus, the following zones are accessible:
The VME slave registers
The Flash memory bank 0
The SRAM memory
The Real-Time Clock device
Accessing one of these zones at the same time from the VMEbus and the host processor starts an
internal arbitration between the two masters and keep the 'loosing' master in a wait state while the
'winning' master can access the zone.
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