Actis VSBC-6872 Series, Руководство пользователя

Страница: 29 / 105

VSBC-6872 series
ACTIS Computer
28
3.12 Direct Memory Access Controller
The PowerQUICC II has two physical serial DMA (SDMA) channels.
The CPM implements two dedicated virtual SDMA channels for each FCC, MCC, SCC, SMC, SPI and I
2
C
−
one for each transmitter and receiver.
An additional four virtual SDMA channels are assigned to the programmable independent DMA (IDMA)
channels.
Figure 9 - DMA block diagram
For detailed specification and register setting, please consult the following literature:
"Freescale literature described in the hardware configuration chapter"
3.13 I
2
C serial interface bus
The MPC8270 processor has an on-chip I
2
C serial bus controller compatible with the Philips specification.
The I
2
C bus has a two-wire, bi-directional, open-drain, low-speed serial interface. The serial clock and
serial data lines are bi-directional, to support multiple bus masters and to mix high- and low-speed
devices on the same bus.
The I
2
C interface supports the following standard and enhanced features:
•
up to 400-kHz operation
•
8-bit data transfers
•
7-bit addressing
•
Slave transmitter and receiver
•
Master transmitter and receiver
•
Multiple bus masters
For detailed specification and register setting, please consult the following literature:
"Freescale literature described in the hardware configuration chapter"
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com