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AR-B1380/AR-1380A User’ s Guide
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Address Description
16 High base memory byte
17 Low expansion memory byte
18 High expansion memory byte
19-2D Reserved
2E-2F 2-byte CMOS checksum
30 Low actual expansion memory byte
31 High actual expansion memory byte
32 Date century byte
33 Information flags (set during power on)
34-7F Reserved for system BIOS
Table 2-5 Real-Time Clock & Non-Volatile RAM
2.6 TIMER
The AR-B1380/AR-B1380A provides three programmable timers, each with a timing frequency of 1.19 MHz.
Timer 0 The output of this timer is tied to interrupt request 0. (IRQ 0)
Timer 1 This timer is used to trigger memory refresh cycles.
Timer 2 This timer provides the speaker tone.
Application programs can load different counts into this timer to generate various sound
frequencies.
2.7 SERIAL PORTS
The ACEs (Asynchronous Communication Elements ACE1 to ACE4) are used to convert parallel data to a
serial format on the transmit side and convert serial data to parallel on the receiver side. The serial format,
in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if
programmed) and one, 1.5 (five-bit format only) or two stop bits. The ACEs are capable of handling
divisors of 1 to 65535, and produce a 16x clock for driving the internal transmitter logic.
Provisions are also included to use this 16x clock to drive the receiver logic. Also included in the ACE a
complete MODEM control capability, and a processor interrupt system that may be software tailored to the
computing time required to handle the communications link.
The following table is a summary of each ACE accessible register
DLAB Port Address Register
Receiver buffer (read) 0 base + 0
Transmitter holding register (write)
0 base + 1 Interrupt enable
X base + 2 Interrupt identification (read only)
X base + 3 Line control
X base + 4 MODEM control
X base + 5 Line status
X base + 6 MODEM status
X base + 7 Scratched register
1 base + 0 Divisor latch (least significant byte)
1 base + 1 Divisor latch (most significant byte)
Table 2-6 ACE Accessible Registers