SERIES IP236A INDUSTRIAL I/O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE
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The information contained in this manual is subject to change
without notice. Acromag, Inc. makes no warranty of any kind with
regard to this material, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose.
Further, Acromag, Inc. assumes no responsibility for any errors
that may appear in this manual and makes no commitment to
update, or keep current, the information contained in this manual.
No part of this manual may be copied or reproduced in any form,
without the prior written consent of Acromag, Inc.
Table of Contents
Page
1.0 GENERAL INFORMATION
...........................................
2
KEY IP236A FEATURES..............................................
3
INDUSTRIAL I/O PACK INTERFACE FEATURES........
3
SIGNAL INTERFACE PRODUCTS...............................
3
INDUSTRIAL I/O PACK SOFTWARE LIBRARY...........
4
IP MODULE VxWORKS SOFTWARE………….……….
4
2.0 PREPARATION FOR USE
............................................
4
UNPACKING AND INSPECTION..................................
4
CARD CAGE CONSIDERATIONS................................
4
BOARD CONFIGURATION...........................................
4
Default Hardware Jumper Configuration......….........
5
Analog Ranges & Corresponding Digital Codes……
5
Analog Output Range Jumper Configuration……….
5
CONNECTORS.............................................................
5
IP Field I/O Connector (P2).......................................
5
Analog: Noise and Grounding Considerations………
6
External Trigger Input/Output………………………….
6
IP Logic Interface Connector (P1)..............................
6
3.0
PROGRAMMING INFORMATION
.................................
7
ADDRESS MAPS..........................................................
7
IDENTIFICATION SPACE............................……..........
7
I/O SPACE ADDRESS MAP.….....................................
7
Channel Software Reset Register......……..……………
8
Start Convert / FIFO Full Status Register………………
8
Interrupt Status Register…………………………….……
8
Interrupt Vector Register………………………………….
8
Calibration Coefficient Access
Register….....................
9
Calibration Coefficient Status Register…...……......…..
9
CHANNEL REGISTERS………………………………….
10
Channel Control / Status Register………………….……
10
Channel Timer Prescaler Register.................................
10
Channel Conversion Timer Register..............................
11
Channel FIFO Buffer Port……………………..................
11
DAC MODES OF CONVERSION..................................
11
Single Conversion
From FIFO Buffer……………..…….
11
Continuous Conversions From FIFO Buffer..........……..
11
Convert On External Trigger Only……..................….....
11
PROGRAMMING CONSIDERATIONS..........................
12
Single Convers
ion Mode Example……………………….
12
Continuous Conversion Mode with Interrupt Example…
12
General Sequence of Events for Processing Interrupt…
12
USE OF CALIBRATION DATA......................................
13
Uncalibrated Pe
rformance……………...........................
13
Calibrated Performance…………………………………..
13
Calibrated Programming Example...................…..........
13
4.0
THEORY OF OPERATION
............................................
14
FIELD ANALOG OUTPUTS..........................................
14
LOGIC/POWER INTERFACE.......................................
14
IP INTERFACE LOGIC……….......................................
14
CONVERSION CONTROL LOGIC………………………
15
DATA TRANSFER FROM FPGA TO DACs..................
15
INTERVAL TIMER…………….......................................
15
EXTERNAL TRIGGER.……….......................................
15
INTERRUPT CONTROL LOGIC…................................
15
CALIBRATION MEMORY CONTROL LOGIC...............
15
5.0
SERVICE AND REPAIR
................................................
16
SERVICE AND REPAIR ASSISTANCE........................
16
PRELIMINARY SERVICE PROCEDURE......................
16
6.0
SPECIFICATIONS
.........................................................
16
PHYSICAL……………………........................................
16
ENVIRONMENTAL………………………………………..
16
ANALOG OUTPUT.......................................................
17
INDUSTRIAL I/O PACK COMPLIANCE........................
17
APPENDIX
....................................................................
18
CABLE: MODEL 5025-550-X. & 5025-551-X.................
18
TERMINATION PANEL: MODEL 5025-552...................
18
TRANSITION MODULE: MODEL TRANS-GP...............
18
DRAWINGS
Page
4501-434 IP MECHANICAL ASSEMBLY......................
19
4501-736 IP236A BLOC
K DIAGRAM....................…....
20
4501-
737 ANALOG OUTPUT CONNECTION..….…....
21
4501-
735 JUMPER LOCATION........…………………...
22
4501-462 CABLE 5025-550 (NON-SHIELDED)............
23
4501-463 CABLE 5025-551 (SHIELDED).....................
24
4501-464 TERMINATION PANEL 5025-552................
25
4501-465 TRANSITION MODULE TRANS-GP.............
26
IMPORTANT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible adverse
effects of power, wiring, component, sensor, or software failures
in designing any type of control or monitoring system. This is
especially important where economic property loss or human life
is involved. It is important that the user employ satisfactory
overall system design. It is agreed between the Buyer and
Acromag, that this is the Buyer's responsibility.
Trademarks are the property of their respective owners.
1.0 GENERAL INFORMATION
The Industrial I/O Pack (IP) Series IP236A modules are
precision 16-bit, high density, single size IP, analog output boards
with up to eight analog voltage output channels. All channels can
be independently controlled allowing unique DAC update rates if
desired. Each of the output channels include generous 128-
sample FIFO buffers, from which digital values are transferred to
its corresponding Digital-to-Analog-Converter (DAC). In addition
to the FIFO, interrupt generation is also supported for FIFO
almost empty conditions, to minimize CPU interaction.
The IP236A modules interface to the VMEbus, PCIbus, or
ISAbus, carrier boards. Up to five units may be mounted on the
PCIbus carrier board to provide up to 40 16-bit independent DAC
output channels per PCI system slot.
The IP236A utilizes state of the art Surface-Mounted
Technology (SMT) to achieve its wide functionality and is an ideal
choice for a wide range of industrial and scientific applications
that require, high-performance analog outputs.
The IP236A modules are available with eight (IP236A-8) 16-
bit analog output channels. The IP236A-8 is available in
standard and extended temperature range modules as follows:
