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SERIES IP236A INDUSTRIAL I/O PACK                           FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE 
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- 5 - 

The board may be configured differently, depending on the 

application.  Jumper settings are discussed in the following 
sections.  The jumper locations are shown in Drawing 4501-735. 

 

Default Hardware Jumper Configuration 

 
The board is shipped from the factory, configured as follows: 

 

Each analog output range is configured for a bipolar output 
with a 20 volt span (i.e. a DAC output range of -10 to +10 
Volts). 

 

The default programmable software control register bits at 
power-up are described in section 3.  The control registers 
must be programmed to the desired mode before starting 
DAC analog output conversions. 

 

Analog Output Ranges and Corresponding Digital Codes 

 
The IP236A is designed to accept positive-

true binary two’s 

complement (BTC) input codes which are compatible with bipolar 
analog output operation.  Table 2.1 indicates the relationship 
between the data format and the ideal analog output voltage for 
each of the analog output ranges. Selection of an analog output 
range is implemented via the jumper setting given in Table 2.2.  

 

Table 2.1: Full-Scale Ranges and Ideal Analog Output 

DESCRIPTION

 

Digital 

Input 
Code

 

ANALOG OUTPUT 

Output Range 

 

10V 

0 to 10V 

5V 

LSB (Least 
Significant Bit) 
Weight 

 

305 V 

153 V 

153 V 

Plus Full Scale 
Minus One LSB 

7FFF

H

 

9.999695 

Volts

 

9.999847

Volts

 

4.999847

Volts

 

Midscale 
 

0000

H

 

0V

1

 

5V

1

 

0V

1

 

One LSB Below 
Midscale 

FFFF

H

 

-305 V 

4.999847

Volts

 

-153 V 

Minus Full 
Scale 

8000

H

 

-10V 

0V 

-5V 

 
Notes (Table2.1):

 

1.   Upon power-up or software reset the bipolar ranges will 

output 0 volts while the unipolar range will output 5 volts. 

 

Analog Output Range Hardware Jumper Configuration 

 

The output range of the DACs are individually programmed 

via hardware jumpers J1 to J8.  Jumpers J1 to J8 are used to 
control channels 0 to 7, respectively.  The jumpers control the 
output voltage span and the selection of unipolar or bipolar output 
ranges.  J1 to J8 pins 1 and 2 control the selection of unipolar or 
bipolar output ranges.  J1 to J8 pins 3 and 4 control the selection 
of output voltage span.  The configuration of the jumpers for the 
different ranges is shown in Table 2.2.  “ON” means that the pins 
are shorted together with a shortin

g clip.  “OFF” means that the 

clip has been removed.  The individual jumper locations are 
shown in Drawing 4501-735. 
 

Table 2.2: Analog Output Range Selections/Jumper Settings 

Desired 

ADC Output 

Range (VDC) 

Output 

Span 

(Volts) 

Required 

Output 

Type 

J1 to J8 

Pins (1&2) 

 

J1 to J8 

Pins (3&4) 

 

-5 to +5 

10 

Bipolar 

ON 

ON 

-10 to +10

1

 

20 

Bipolar 

ON 

OFF 

0 to +10 

10 

Unipolar 

OFF 

ON 

 
Notes (Table2.2):

 

1.   The board is shipped with the default jumper setting for the 

10 volt DAC output range. 

 
Software Configuration 

 

Software configurable control registers are provided for 

control of external trigger mode, conversion mode, timer control, 
and interrupt mode selection.  No hardware jumpers are required 
for control of these functions.  These control registers must also 
be configured as desired before starting DAC analog output 
conversions.  Refer to section 3 for programming details.  
 

CONNECTORS 

 
Connectors of the IP236A module consist of one IP module 

field I/O connector, and one IP module logic connector.  These 
interface connectors are discussed in the following sections. 

 

IP Field I/O Connector (P2) 

 

P2 provides the field I/O interface connections for mating IP 

modules to the carrier board.  P2 is a 50-pin female receptacle 
header (AMP 173279-3 or equivalent) which mates to the male 
connector of the carrier board (AMP 173280-3 or equivalent).  
This provides excellent connection integrity and utilizes gold-
plating in the mating area.  Threaded metric M2 screws and 
spacers are supplied with the module to provide additional 
stability for harsh environments (see Mechanical Assembly 
Drawing 4501-434).  The field and logic side connectors are 
keyed to avoid incorrect assembly. 

 
P2 pin assignments are unique to each IP model (see Table 

2.3) and normally correspond to the pin numbers of the field I/O 
interface connector on the carrier board (you should verify this for 
your carrier board).  When reading Table 2.3 note that channel 
designations are abbreviated to save space.  For example, 
channel 0 is abbreviated as “+CH00” & “-CH00” for the + & - 
connections, respectively.  Further, note that the output signals 
all have the same ground reference (“-CH00” and the minus leads 
of all other channels are connected to analog common on the 
module). 

 

Содержание IP236A Series

Страница 1: ...tput Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 295 0310 Fax 248 624 9234 Copyright 1999 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 889 B11M004 ...

Страница 2: ...TERFACE LOGIC 14 CONVERSION CONTROL LOGIC 15 DATA TRANSFER FROM FPGA TO DACs 15 INTERVAL TIMER 15 EXTERNAL TRIGGER 15 INTERRUPT CONTROL LOGIC 15 CALIBRATION MEMORY CONTROL LOGIC 15 5 0 SERVICE AND REPAIR 16 SERVICE AND REPAIR ASSISTANCE 16 PRELIMINARY SERVICE PROCEDURE 16 6 0 SPECIFICATIONS 16 PHYSICAL 16 ENVIRONMENTAL 16 ANALOG OUTPUT 17 INDUSTRIAL I O PACK COMPLIANCE 17 APPENDIX 18 CABLE MODEL 5...

Страница 3: ...s are set for bipolar operation the analog outputs are reset to 0 volts upon power up or receipt of a software or hardware reset This eliminates the problem of applying random output voltages to actuators during power on sequences Hardware Jumper Setting For Selection of DAC Ranges Both bipolar 5V 10V and unipolar 0 to 10V ranges are available The ranges can be selected on a per channel basis High...

Страница 4: ...ode to make possible simple control of all Acromag PCI boards 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and...

Страница 5: ...tion of output voltage span The configuration of the jumpers for the different ranges is shown in Table 2 2 ON means that the pins are shorted together with a shorting clip OFF means that the clip has been removed The individual jumper locations are shown in Drawing 4501 735 Table 2 2 Analog Output Range Selections Jumper Settings Desired ADC Output Range VDC Output Span Volts Required Output Type...

Страница 6: ...and grounding connections External Trigger Input Output Signals The external trigger signals on pins 42 to 49 of the P2 connector can be programmed to accept a TTL compatible external trigger input signal or output hardware timer generated triggers to allow synchronization of multiple IP236A modules As an input the external trigger must be a 5 Volt logic TTL compatible debounced signal referenced ...

Страница 7: ... 1 IP236A ID Space Identification Format I Hex Offset From ID Base Address ASCII Character Equivalent Numeric Value Hex Field Description 01 I 49 All IP s have IPAC 03 P 50 05 A 41 07 C 43 09 A3 Acromag ID Code 0B 26 IP236A 8 IP Model Code1 0D 00 Not Used Revision 0F 00 Reserved 11 00 Not Used Driver ID Low Byte 13 00 Not Used Driver ID High Byte 15 0C Total Number of ID PROM Bytes 17 93 IP236A 8 ...

Страница 8: ...tiated 6 625 seconds after setting its corresponding Start Convert Bit Start Convert FIFO Full Status Register MSB LSB 07 06 05 04 03 02 01 00 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 When read this register is used to reflect the FIFO full status of the individual channel FIFO buffers The individual bits used to indicate FIFO Full status for each of the channel FIFOs is shown in the previous table A set b...

Страница 9: ...libration Coefficient Status register is a read only register and is used to access the calibration coefficient read data and determine the status of a read cycle initiated by the Calibration Coefficient Access register In addition this register is used to determine the status of a write cycle to the coefficient memory When set bit 1 of this register indicates the coefficient memory is busy comple...

Страница 10: ... be wired together for all channels modules to be synchronized The External Trigger input can be sensitive to external EMI noise which can cause erroneous external triggers If External Trigger Inputs are not required the External Trigger should be configured as an output BIT FUNCTION 4 0 Disable Interrupt 1 Enable Interrupt An interrupt request from the IP236A will be issued to the system if enabl...

Страница 11: ...hardware reset It is recommended that interrupts be enabled for a FIFO almost empty condition 64 16 or 4 samples or less left in the FIFO Upon this interrupt no more then 128 samples minus the threshold value 64 16 or 4 should be written to the FIFO Write accesses to this register typically require two wait states and can be a maximum of 4 wait states when the write overlaps with a FIFO read for D...

Страница 12: ...rier board documentation for compatibility details 1 Clear the global interrupt enable bit in the carrier board status register by writing a 0 to bit 3 2 Write the interrupt vector to the IP236A Module at base address 03H 3 Write to the carrier board interrupt Level Register to program the desired interrupt level per bits 2 1 0 4 Write 1 to the carrier board IP Interrupt Clear Register correspondi...

Страница 13: ... to the DAC channel to accurately generate the desired output voltage See the specification chapter for details regarding maximum calibrated error Data is corrected using a couple of formulas Equation 1 expresses the ideal relationship between the value Ideal_count written to the 16 bit DAC to achieve a specified voltage within the selected output range Equation 1 Ideal_ Count Count_ Span Desired_...

Страница 14: ... value is rounded to 8 197 and is equivalent to DFFB hex as a 2 s complement value 6 Execute Write of DFFB hex to the Channel 0 s FIFO Buffer port at Base Address 0CH 7 Execute Write of 0001H to the Start Convert Bit at Base Address 00H This starts the transfer of the digital data in Channel 0 s FIFO buffer to its corresponding DAC for analog conversions This will drive channel 0 s analog output t...

Страница 15: ...ted via two programmable counters an 8 bit Timer Prescaler and a 16 bit Conversion Timer The Timer Prescaler is clocked by the 8MHz board clock The output of the Timer Prescaler is then used to clock the Conversion Timer In this way the two counters are cascaded to provide variable time periods anywhere from 6 6 seconds to 2 0889 seconds The output of this interval counter is used to trigger the s...

Страница 16: ...CC rise time 100m Seconds Power IP236A Requirements 8 8E 5V Typical 92mA 5 Max 120mA 12V Typical 130mA 5 Max 170mA 12V Typical 160mA 5 Max 210mA ENVIRONMENTAL Operating Temperature Standard Unit 0 to 70 C E suffixed units 40 C to 85 C Note The extended temperature grade version of the DAC714 is no longer available from the manufacturer Acromag has performed operational tests of sampled commercial ...

Страница 17: ... is 0 2 FSR i e 20V SPAN max Gain Error is 0 25 maximum Settling Time 10uS to within 0 003 of FSR for a 20V step change load of 5K in parallel with 500pF Conversion Rate per channel 150KHz Maximum 100KHz recommended for specified accuracy Output Noise 120 nV Hz typical Output at Reset Bipolar Zero Volts Unipolar 5 Volts See Note 5 Board Warm up Time 10 minutes minimum Note 5 The hardware reset fun...

Страница 18: ...Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to AVME9630 9660 APC8610 or APC8620 P1 50 pin male header with strain relie...

Страница 19: ...D TIGHTEN 4 PLACES THE RECOMMENDED TORQUE IS 0 226 NEWTON METER OR 2 INCH POUNDS OVER TIGHTENING MAY DAMAGE CIRCUIT BOARD 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF IP MODULE AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES UNTIL HEX SPACER IS COMPLETELY SEATED THE RECOMMENDED TORQUE IS 0 226 NEWTON METER OR 2 INCH POUNDS OVER TIGHTENING MAY DAMAGE CIRCUIT BOARD 1 THREADED SPACERS ARE...

Страница 20: ...SERIES IP236A INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 20 ...

Страница 21: ...SERIES IP236A INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 21 ...

Страница 22: ...SERIES IP236A INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 22 ...

Страница 23: ...SERIES IP236A INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 23 ...

Страница 24: ...SERIES IP236A INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 24 ...

Страница 25: ...SERIES IP236A INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 25 ...

Страница 26: ...SERIES IP236A INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 26 ...

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