SERIES IP236A INDUSTRIAL I/O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE
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The Single Conversion mode of operation is used in this
example.
1.
Execute Write of 02H to Channel Control Register at Base
A 09H.
a)
External, and Software triggers are enabled.
b)
Single Conversion mode is enabled.
2.
Read the calibration memory to retrieve channel 0’s unique
offset coefficient. To obtain the 16-bit offset coefficient, two
read accesses of the coefficient memory are required. To
initiate a read of channel 0’s most significant byte of the
offset coefficient, the Calibration Coefficient Access register
must be written with data value 8000H at Base A
04H. The offset coefficient can be read by polling the
Calibration Coefficient Status register. When bit 0 of the
Calibration Coefficient Status register is set to logic high,
then the data on bits 15 to 8 contain the most significant
byte of the offset coefficient.
To initiate a read of channel 0’s least significant byte of the offset
coefficient, the Calibration Coefficient Access register must
be written with data value 8100H at Base A 04H.
When bit 0 of the Calibration Coefficient Status register is
set to logic high, then the data on bits 15 to 8 of this register
contains the least significant byte of the offset coefficient.
3.
Read the calibration memory to retrieve channel 0’s unique
16-bit gain coefficient. To obtain the 16-bit gain coefficient,
two read accesses of the coefficient memory are required.
To initiate a read of channel 0’s most significant byte of the
gain coefficient, the Calibration Coefficient Access register
must be written with data value 8200H at Base A
04H. The gain coefficient can be read by polling the
Calibration Coefficient Status register. When bit 0 of the
Calibration Coefficient Status register is set to logic high,
then the data on bits 15 to 8 contains the most significant
byte of the gain coefficient.
To initiate a read of channel 0’s least significant byte of the gain
coefficient, the Calibration Coefficient Access register must
be written with data value 8300H at Base A 04H.
When bit 0 of the Calibration Coefficient Status register is
set to logic high, then the data on bits 15 to 8 of this register
contains the least significant byte of the gain coefficient.
4.
Calculate the Ideal_Count required to provide an
uncorrected output of the desired value (-2.5 Volts) by using
equation (1).
Ideal_Count =
[65,536 (-2.5)]/20 = -8,192.0
5.
Calculate the Corrected_Count required to provide an
accurate output of the desired value (-2.5 Volts) by using
equation (2). Assume the offset and gain coefficients are -
43 and -185 respectively.
Corrected_Count =
-8,192.0 [1 + -185/(4 65,536)] - 43/4 =
-8,196.9687. This value is rounded to -8,197 and is
equivalent to DFFB hex as a 2’s complement value.
6.
Execute Write of DFFB hex to the Channel 0’s FIFO Buffer
port at Base A 0CH.
7.
Execute Write of 0001H to the Start Convert Bit at Base
A 00H. This starts the transfer of the digital data in
Channel 0’s FIFO buffer to its corresponding DAC for analog
conversions. This will drive channel 0’s analog output to -
2.5 volts.
8.
(OPTIONAL) Observe or monitor that the specific DAC
channel (0) reflects the results of the digital data converted
to an analog output voltage at the field connector.
Error checking should be performed on the calculated count
values to insure that calculated values below 0 or above 65535
decimal are restricted to those end points. Note that the software
calibration cannot generate outputs near the endpoints of the
range which are clipped off due to hardware limitations(i.e. the
DAC).
4.0 THEORY OF OPERATION
This section contains information regarding the hardware of
the IP236A. A description of the basic functionality of the circuitry
used on the board is also provided. Refer to the Block Diagram
shown in Drawing 4501-736 as you review this material.
FIELD ANALOG OUTPUTS
The field I/O interface to the carrier board is provided through
connector P2 (refer to Table 2.3).
Field I/O signals are NON-
ISOLATED.
This means that the field return and logic common
have a direct electrical connection to each other. As such, care
must be taken to avoid ground loops (see Section 2 for
connection recommendations). Ignoring ground loops may cause
operation errors, and with extreme abuse, possible circuit
damage. Refer to Drawing 4501-737 for example wiring and
grounding connections.
Jumpers on the board control the range selection for the
DACs (-5 to +5, -10 to +10, and 0 to 10 Volts) as detailed in
chapter 2. Jumper selection should be made prior to powering
the unit. Channels may use different ranges.
LOGIC/POWER INTERFACE
The logic interface to the carrier board is made through
connector P1 (refer to Table 2.4). The P1 interface also provides
+5V and 12V power to the module. Note that the DMA control,
INTREQ1 , ERROR , and STROBE signals are not used.
A Field Programmable Gate-Array (FPGA) installed on the IP
Module provides an interface to the carrier board per IP Module
specification ANSI/VITA 4 1995. The interface to the carrier
board allows complete control of all IP236A functions.
IP INTERFACE LOGIC
IP interface logic of the IP236A is imbedded within the FPGA.
This logic includes: address decoding, I/O and ID read/write
control circuitry, and ID storage implementation.
Address decoding of the six IP address signals A(1:6) is
implemented in the FPGA, in conjunction with the IP select
signals,
to identify access to the IP module’s ID or I/O space. In
addition, the byte strobes BS0 and BS1 are decoded to identify
low byte, high byte, or double byte data transfers.
The carrier to IP module interface implements access to both
ID and I/O space via 16 or 8-bit data transfers. Read only access
