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SERIES  I/O SERVER MODULE

 

MIL-STD-1553A/B Bus Interface Module 

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Acromag, Inc. Tel:248-295-0310  Fax:248-624-9234     Email:[email protected]  

www.acromag.com 

To select the external time tag clock input as the Micro ACE time tag clock:  write bits 
TTR2:0 in configuration register #2 with the bit pattern “111”.   Write the tag clock source 
(bit 7) of the IOS I/O space control register with the value 1. 

Note: the selection of tag clock source in the IOS I/O space control register will affect both 
1553 channels of an IOS-572 module. 

STATIC MICRO ACE INPUTS 

The SUBSYSTEM/EXT_TRIG Micro ACE input signal is permanently connected to logic 1 
in the FPGA. The functions controlled by this static input signal have alternate methods of 
control through host writes to Micro ACE registers.  The subsystem flag bit can be set by 
the host writing to bit 8 of Configuration Register #1 in RT mode.  In BC mode, a frame can 
be started by writing bit 1 of the Start/Reset Register with the value 1. 

REMOTE TERMINAL ADDRESS 

The RT address and parity signals for each of the 1553 channels are available at the P2 
connector.  Each of the signals has an adjacent ground signal on the connector for 
convenient programming of the RT address through an attached wire harness.  Each of the 
address lines and parity bit has a pull up resistor on it.  An unconnected input results in that 
bit reading as logic 1.  Grounding the input causes the bit to read as logic 0.  The RT 
address parity is odd, so the sum of the RT address input bits and the RT parity bit must be 
odd.  The RT address may be latched in the Micro ACE.  The RT address latch signal is 
controlled by the IOS I/O control register.  Bit 9 controls the RT address latch signal for 
channel 1, bit 1 controls the RT address latch signal for channel 0.  

See section 6.29 RT Address Inputs of the Enhanced Mini-ACE® Series Users Guide for a 
complete description of the options available for setting the RT address.  

BUS CONNECTION 

The IOS-57x modules may be connected to the1553 bus using either of two methods: 
direct coupled (short stub) or transformer coupled (long stub).  Both of these connection 
methods are provided for both of the dual redundant (A and B) channels of each of the 
1553 channels (0 and 1). 

DIRECT COUPLING METHOD 

Using the direct coupling method the IOS-57x module may be connected to the 
1553 bus without any additional components.  The transformer and isolation 
resistors are included on the IOS-57x.  The stub length may not exceed 1 foot.  
The distance the signals travel across a carrier board must be subtracted from the 
1 foot maximum length. 

TRANSFORMER COUPLING METHOD 

Using the transformer coupling method, stub lengths may be up to 20 feet.   With 
this method the IOS-57x does not connect directly to the 1553 bus.  The IOS-57x 
must connect to the bus through a bus coupler. 

Transformer coupling provides improved thermal performance when compared with direct 
coupling since the heat dissipated in the isolation resistors is located outside of the I/O 
Server. 

SERVICE AND REPAIR 

Surface-Mounted Technology (SMT) boards are generally difficult to repair. It is highly 
recommended that a non-functioning board be returned to Acromag for repair. The board 
can be easily damaged unless special SMT repair and service tools are used. Further, 

Содержание IOS-571

Страница 1: ...rface Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2010 2011 Acromag Inc Pri...

Страница 2: ...UNPACKING AND INSPECTION 6 INSTALLATION 6 CONNECTORS 6 Field I O Connector P2 6 CABLE 7 Non Isolation Considerations 8 PROGRAMMING INFORMATION 8 IDENTIFICATION PROM 8 ADDRESS MAP 9 I O SPACE ADDRESS M...

Страница 3: ...PUBLICATIONS The following manuals and part specifications provide the necessary information for in depth understanding of the IOS 57x Series boards These documents are available on the Data Device C...

Страница 4: ...les may be installed in an I O Server if all channels are operating in monitor mode transmitter duty cycle is 0 KEY FEATURES One or two dual redundant MIL STD 1553A B channels Each channel can be inde...

Страница 5: ...e DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers I O SERVER Linux SOFTWARE Acromag pro...

Страница 6: ...le shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an an...

Страница 7: ...CK_IN 8 GND 33 GND 9 GND 34 GND 10 CH1B_DIRECT_N 35 CH1B_XFMR_N 11 CH1B_DIRECT_P 36 CH1B_XFMR_P 12 GND 37 GND 13 GND 38 GND 14 CH1A_DIRECT_N 39 CH1A_XFMR_N 15 CH1A_DIRECT_P 40 CH1A_XFMR_P 16 GND 41 GN...

Страница 8: ...connections PROGRAMMING INFORMATION This Section provides the specific information necessary to program and operate the board IDENTIFICATION PROM Each IOS module contains identification ID information...

Страница 9: ...CRC 8F IOS 571 EE IOS 572 18 to 3E yy Not Used Note Table 4 1 The model number is represented by a two digit code within the ID space the IOS 571 model is represented by 52H the IOS 572 is represente...

Страница 10: ...it A 0 4 Channel 0 Transceiver Inhibit B 0 3 Channel 0 Master Clear 0 2 Channel 0 Built In Self Test Enable 0 1 Channel 0 Remote Terminal Address Latch 0 0 Channel 0 Interrupt Enable 0 IOS bus clock A...

Страница 11: ...is connected to IRQ0 Channel 1 interrupt is connected to IRQ1 MEMORY SPACE ADDRESS MAP This board is addressable in memory space to access the Micro ACE 1553 controllers The IOS 571 uses the lower 256...

Страница 12: ...er 5 RD WR 00014 RT Monitor Data Stack Address Register RD 00016 BC Frame Time Remaining Register RD 00018 BC Time Remaining to Next Message Register RD 0001A Non Enhanced BC Frame Time Enhanced BC In...

Страница 13: ...gister 2 to select LEVEL type interrupt signaling for each channel This will enable the FPGA to pass the Micro ACE interrupt signal through to the IOS bus INTREQx interrupt See the Enhanced Mini ACE S...

Страница 14: ...IC All logic to provide access to the Micro ACE 1553 controllers is imbedded in the module s FPGA Once the IOS 57x FPGA has been configured the control logic provides the following functions Source of...

Страница 15: ...its and the RT parity bit must be odd The RT address may be latched in the Micro ACE The RT address latch signal is controlled by the IOS I O control register Bit 9 controls the RT address latch signa...

Страница 16: ...eded complete repair services are also available from Acromag WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag co...

Страница 17: ...EN50082 1 Electric Fast Transient Immunity EFT Complies IEC 6100 4 4 2007 Electrostatic Discharge ESD Immunity Complies with IEC 61000 4 2 2001 8KV enclosure port air discharge Level 3 4KV enclosure...

Страница 18: ...x Unit CHx_RT_ADDRx CHx_RT_PARITY VIL low level input voltage 0 6 V VIH high level input voltage 2 0 3 3 V IIL low level current VIL 0 V 330 A TAG_CLK_IN VIL low level input voltage 0 8 V VIH high lev...

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