SERIES I/O SERVER MODULE
MIL-STD-1553A/B Bus Interface Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected]
www.acromag.com
Tag Clock Source
:
0
– internal (FPGA 100 KHz clock)
1
– external (P2 connector)
Table 7 Status Register Read I/O base a 2
Bit
Description
15
Module Clock Ready
14
Not used
13
Not used
12
Not used
11
Not used
10
Not used
9
Not used
8
Channel 1 Interrupt Pending
7
Not used
6
Not used
5
Not used
4
Not used
3
Not used
2
Not used
1
Not used
0
Channel 0 Interrupt Pending
Module Clock Ready
– Indicates the status of the phase locked loop that generates the 16
MHz module clock from the IOS bus clock:
0 - not ready
1 - ready
Interrupt Pending
0
– no interrupts pending
1
– interrupt pending
Channel 0 interrupt is connected to IRQ0
Channel 1 interrupt is connected to IRQ1
MEMORY SPACE ADDRESS MAP
This board is addressable in memory space to access the Micro ACE 1553 controllers.
The IOS-571 uses the lower 256K bytes of this memory space to access channel 0
registers and memory. The IOS-572 uses the lower 512K bytes of this memory space to
access channels 0 and 1 registers and memory.
Micro ACE access
The address space for each Micro ACE is divided into two regions: register and memory.
The 32 Micro ACE registers are located at IOS memory space base a (channel *
0x40000) + (register address * 2). The Micro ACE also includes 64 K 16 bit words of
memory. The memory region is located at IOS memory space base a (channel *
0x40000) + 0 memory address. The Micro ACE is a 16 bit device and should be
accessed in 16 bit mode. See Table 8 for a brief overview of the Micro ACE registers and
their addresses in IOS memory space. See the Enhanced Mini-ACE® Series Users Guide
for a detailed description of the registers and their functions.
