SERIES I/O SERVER MODULE
MIL-STD-1553A/B Bus Interface Module
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Mem base +
Address (Hex)
Description
CHANNEL 1
40000
Interrupt Mask Register #1 (RD/WR)
40002
Configuration Register #1 (RD/WR)
40004
Configuration Register #2 (RD/WR)
repeat of Channel 0 register descriptions
4003E
BC General Purpose Queue Pointer /RT-MT Interrupt Status Queue
Pointer Register (RD/WR)
60000
7FFFE
Channel 1 RAM first word
Channel 1 RAM last word
PROGRAMMING INTERRUPTS
Interrupts generated by the IOS-57x modules use interrupt request lines INTREQ0*
(Interrupt Request 0) for 1553 channel 0 and INTREQ1* (Interrupt Request 1) for 1553
channel 1.
The IOS-57x Interrupt Vector register can be used as a pointer to an interrupt handling
routine. The vector is an 8-bit value and can be used to point to any one of 256 possible
locations to access the interrupt handling routine.
To enable 1553 channels to generate interrupts set the appropriate interrupt enable bit in
the IOS I/O space Control Register for each 1553 channel. Set bit 3 in the Micro ACE
Configuration Register #2 to select LEVEL type interrupt signaling for each channel. This
will enable the FPGA to pass the Micro ACE interrupt signal through to the IOS bus
INTREQx interrupt. See the Enhanced Mini-ACE® Series Users Guide for details on
configuring the many Micro ACE interrupt options.
The INTREQ0* or INTREQ1* line is released when the INTERRUPT STATUS
REGISTER(s) for the appropriate channel are read. See the Enhanced Mini-ACE® Series
Users Guide for details on AUTO CLEAR options for the pending interrupts.
THEORY OF OPERATION
This section contains information regarding the hardware of the IOS-57x series of modules.
A description of the functions of the circuitry used on the board is also provided. Refer to
Figure 1, IOS-572 block diagram as you review this material.
LOGIC/POWER INTERFACE
The logic interface to the carrier board is made through connector P1 (refer to
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). The P1 interface also pr5V power to the module.
Note that the DMA control, ERROR , and STROBE signals are not used.
A Field Programmable Gate-Array (FPGA) installed on the IOS Module provides an
interface to the carrier board. The interface to the carrier board allows complete control of
all IOS-57x functions.
IOS INTERFACE LOGIC
IOS interface logic of the IOS-57x is included in the FPGA. This logic includes: address
decoding, I/O and ID read/write control circuitry, and ID PROM implementation.
