SERIES IOS-440 I/O SERVER MODULE 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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3. We need to enable the 8MHz system clock to generate our
debounce time. By default, the debounce clock is not
enabled. Select the 8MHz system clock as the debounce
clock by writing 01H to the port 3 address of this bank
(Debounce Clock Select Register). T
his set is not required
for the IOS-440.
4. The default debounce duration is 4us with the 8MHz clock
enabled in step 3. This time applies to the FPGA input signal
and does not include opto-coupler delay. Write 01H to the
port 1 address of this bank to select a 64us debounce time
(Debounce Duration Register 0). An incoming signal must be
stable for the entire debounce time before it will be
recognized as a valid input transition by the FPGA.
Note that Debounce Duration Register 1 (port address 2)
would be used to configure debounce durations for ports 4 &
5. Since ports 4 & 5 are not used by this model, Debounce
Duration Register 1 has no effect.
5. Enable the debounce circuitry for port 0 inputs by setting bit 0
of the Debounce Control Register. Write 01H to the Port 0
address of this bank (Debounce Control Register).
If the module had been configured earlier, you would first
read this register to check the existing settings of debounce
enable for the other ports of this module with the intent of
preserving their configuration by adjusting the value written
above.
6. Write 40H to the port 7 address to select register bank 1
where the event polarity requirements of our application will
be configured.
At this point, you are in Enhanced Mode Bank 1 where
access to the event polarity/status registers is obtained.
7. For change-of-state detection, both positive and negative
polarities must be sensed. As such, two channels are
required to detect a change-of-state on a single input signal.
For our example, IN00-IN03 will be used to detect positive
events (low-to-high transitions); IN04-IN07 will be used to
detect negative events (high-to-low transitions). Write 02H to
the port 6 address to set IN00-IN03 to positive edge
detection, and IN04-IN07 to negative edge detection.
Note that this port address has a dual function depending on
whether a read or write is being executed. As such, if the
current polarity configuration for the other ports must be
preserved, then it must be remembered since it cannot be
read back.
8. To enable event sensing for the port 0 input points, write FFH
to the Event Sense Status Register for port 0 input points at
the port 0 address in this bank.
Note that writing a 1 to a bit position enables the event sense
detector, while writing a 0 clears the event sensed without
enabling further event sensing.
9. Write 00H to the port 7 address to select register bank 0
where the port 0 input channels may be write-masked.
Note that the port 7 address bank selection only operates
from bits 6 & 7 of this register. Likewise, this register has a
dual function depending on whether a read or write is
executed. As such, the polarity settings cannot be read back
and must be remembered if they are to be preserved for
successive writes.
At this point, you are in Enhanced Mode Bank 0 where
access to the write-mask register is obtained.
10. For our example, port 0 input points are to be used for inputs
only and writes to this port should be masked to prevent the
possibility of data contention between the built-in output
circuitry and the devices driving these inputs. Write 01H to
the port 7 address to mask writes to port 0.
11. Read 01H from the port 7 address to verify bank 0 access
(bits 6 & 7 are 0) and port 0 write masking (bit 0 is 1).
12. (OPTIONAL) Write your interrupt vector to the Interrupt
Vector Register Address (Note that this register operates
independent of the current bank since it does not reside at
any of the bank addresses).
13. (OPTIONAL) Write 01H to the Interrupt Enable Register
(IER) address location to enable IOS control of the IOS
Interrupt Request 0 line (IntReq0).
When a change-of-state is detected, IntReq0 will be pulled
low (if the event sense detection circuitry has been enabled
and IER bit 0=1). In response, the host will execute an
Interrupt Select cycle and the contents of the Interrupt Vector
Register will be provided. To enable further interrupts for an
event that has already occurred at an input point, the Event
Sense Status Register must be written with a 1 to re-enable
event sensing for subsequent events (only after first writing 0
to the corresponding bit position to clear the event sense
flip/flop).
Note that the state of the inputs (on/off) can be determined by
reading the corresponding port address while in bank 0 of the
Enhanced Mode. However, the event sense status can only
be determined by reading the corresponding port address
while in bank 1 of the Enhanced Mode. Remember, the
event sense status is a flag that is raised when a specific
positive or negative transition has occurred for a given input
point, while the state refers to its current level.
4.0 THEORY OF OPERATION
This section provides a description of the basic functionality
of the circuitry used on the board. Refer to the IOS-440 BLOCK
DIAGRAM as you review this material.
IOS-440 OPERATION
The IOS-440 is built around a Field-Programmable Gate
Array (FPGA) IC. The device provides the control interface
necessary to operate the module, the IOS identification space, all
registers, and provides I/O interface and configuration functions.
The FPGA monitors and controls the functions of the 32 digital
inputs used by this model. It also provides debounce control and
event sensing functions.
