SERIES AP48X ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 49 -
http://www.acromag.com
- 49 -
https://www.acromag.com
One-Shot Pulse Mode
One-Shot pulse mode provides an output pulse that is asserted one time or
repeated each time it is re-triggered. One-Shot generation is selected by
setting Counter Control Register bits 2 to 0 to logic “111”.
The Counter Constant A value controls the time until the pulse goes active.
The duration of the pulse high or low is set via the Counter Constant B value.
Note that the Constant B value defines the logic high pulse width, if active
high output is selected, and a low pulse if active low output is selected.
The counter goes through a full countdown sequence for each Counter
Constant value. When the 0 count is detected, on the next rising-edge of
the clock, the output toggles to the opposite state, and the Counter
Constant B value is loaded into the counter and countdown resumes,
decrementing by one each clock cycle. For example, a counter constant
value of 7 will provide a pulse duration of 7 clock cycles of the selected
clock, then 16ns will be added for the count detection of 0.
InA can be used as a Gate-Off signal to stop and start the counter and, thus
output. When InA is enabled via bits 5 and 4 of the control register for
active low Gate-Off input, a logic low input will enable the one-shot counter
while a logic high will stop the one-shot counter. When InA is enabled for
active high Gate-Off operation, a logic high will enable the one-shot counter
while a logic low will stop the one-shot counter.
InB can be used to input an external clock for use in One-Shot Pulse mode.
Bits
7 and 6 must be set to either logic “01” or “10”. Additionally, the clock
source bits 12, 11,
and 10 must be set to logic “110” to enable external clock
input. One-Shot Pulse mode can also select an internal clock enabled
frequency using control register bits 12, 11, and 10.
InC can be used to externally trigger One-Shot pulse mode. Additionally, a
one-shot pulse can be triggered internally via the Counter Trigger Register.
An initial trigger, software or external, causes the one-shot signal to be
generated with no additional triggers required. Additional triggers must not
be input until the one shot pulse has completed count down of the Constant
B value.
If interrupts are enabled via the Enable/Disable Interrupts Register, an
interrupt is generated when the pulse transitions from low to high and also
when the pulse transitions from high to low. The interrupt will remain
pending until released by setting the required bit of the Interrupt
Status/Clear
register.
