manualshive.com logo in svg

Acromag AcroPack AP48 Series, Руководство пользователя, Страница: 57 / 70

Поделиться
Скачать
Acromag AcroPack AP48 Series Скачать руководство пользователя страница 57

SERIES AP48X ACROPACK  

USER

’S MANUAL 

 

 

 

Acromag, Inc. Tel: 248-295-0310  

 

          - 56 -                                    

- 56 - 

https://www.acromag.com 

 

4.0   THEORY OF OPERATION 

 

 

This section contains information regarding the hardware of the AP48X.  A 
description of the basic functionality of the circuitry used on the board is 
also provided.  Refer to the Figures 1 to 3 Block Diagrams for the AP48X 
shown at the end of the manual as you review this material. 

4.1   Counter Timer  

 

Counter timer input control signals are TTL or RS422/RS485 logic level and 
InA, InB, and InC are available via the field connector.  See Table 2.1 to 2.3 
for the list of these signals and their corresponding pin assignments. 

 

Counter timer out signals OUT1 to 10 are TTL or RS422/RS485 logic level and 
are available via the field I/O connector.  See Table 2.1 to 2.3 for the output 
signals and their corresponding pin assignments. 

4.2   Digital Input/Output 

 

Digital input/output signals to the FPGA are buffered using TTL drivers.  Field 
inputs to these buffers include a 4.7K pullup resistor to +3.3V. Output 

operation is considered ‘Fail

-

safe’.  That is, the Digital Input/Output signals 

are always configured as input upon FPGA configuration during power-up.  
This is done for safety reasons to ensure reliable control under all 
conditions.  Once configured the Digital Output channels will be set as 
output signals. 

4.3   Mini PCIe Interface 

 
 

The Mini PCIe interface to the carrier board is made through 52-pin 
connector (refer to Table 2.4).  These connectors also p3.3V power 
and JTAG signals to the module. 

4.4   PCIe Interface Logic 

 
 

The PCIe bus interface logic is embedded within the FPGA.  This logic 
includes support for PCIe commands, including: configuration read/write, 
and memory read/write.  In addition, the PCIe target interface uses a single 
4K base address register, and implements target abort, retry, and 
disconnect.  The AP48X logic also implements interrupt requests via the PCIe 
bus.  
A FPGA device provides the control signals required to operate the board.  It 
decodes the selected addresses, control signals, and interrupt handling.  It 
also returns the acknowledgement messages required by the carrier/CPU 
board per the PCIe specification.  The program for the FGPA is stored in 
separate Flash memory and loaded upon power-up. 
 

Содержание AcroPack AP48 Series

Страница 1: ...SER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email Solutions acromag com Copyright 2016 Acromag Inc Printed in the USA Data and specifications ar...

Страница 2: ...ion 6 1 3 2 Key Features 6 1 3 3 Key Features PCIe Interface 8 1 4 Signal Interface Products 8 1 5 Software Support 8 Windows 9 VxWorks 9 Linux 9 1 6 References 9 2 0 PREPARATION FOR USE 10 2 1 Unpack...

Страница 3: ...rupt Enable Register 29 Counter Trigger Register Write BAR0 0x0000 0010 30 Table 3 7 Counter Trigger Register 30 Counter Stop Register Write BAR0 0x0000 0014 31 Table 3 8 Counter Stop Register 31 Load...

Страница 4: ...ite 52 Digital Input Register Read Only BAR0 0x0000 0160 53 Table 3 20 Digital Input Register 53 Digital Output Register Read Write BAR0 0x0000 0164 53 Table 3 21 Digital Output Register 53 XADC Statu...

Страница 5: ...Humidity 59 6 3 2 2 Isolation 59 6 3 3 Vibration and Shock Standards 59 6 3 4 EMC Directives 59 6 4 Reliability Prediction 60 AP482E LF 60 AP483E LF 60 AP484E LF 60 6 5 Counter Timers 60 6 6 PCIe Bus...

Страница 6: ...reproduced in any form without the prior written consent of Acromag 1 2 1 Trademark Trade Name and Copyright Information 2016 by Acromag Incorporated All rights reserved Acromag and Xembedded are reg...

Страница 7: ...al I O applications that require a high density highly reliable high performance interface at a low cost The counters can be configured for quadrature position measurement pulse width modulated output...

Страница 8: ...input pulses or events A gate off signal is provided to control count up or count down with each event Interrupt generation upon programmed count condition is available Frequency Measurement Each cou...

Страница 9: ...se Specification v2 1 compliant PCI Express Endpoint 1 4 Signal Interface Products This AcroPack Module will mate directly to all Acromag AP carriers Once connected the module is accessed via a front...

Страница 10: ...This software Model APSW API VXW is composed of VxWorks real time operating system libraries for all AcroPack modules VPX I O board products and PCIe I O Cards The software is implemented as a librar...

Страница 11: ...r radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty 2 1 Unpack...

Страница 12: ...adequate thermal conduction must be provided to prevent a temperature rise above the maximum operating temperature 2 3 Board Configuration Power should be removed from the board when installing AP mod...

Страница 13: ...solation 3 3 5 10 In4_A 37 28 6 9 In5_A 12 Reserved isolation 11 Reserved isolation 4 4 7 14 In6_A 38 29 8 13 In7_A 16 Reserved isolation 15 Reserved isolation 5 5 9 18 In8_A 39 30 10 17 In9_A 20 Rese...

Страница 14: ..._C 48 39 28 53 In7_C 56 Reserved isolation 55 Reserved isolation 15 15 29 58 In8_C 49 40 30 57 In9_C 60 Reserved isolation 59 Reserved isolation 16 16 31 62 Din0 50 41 32 61 Din1 64 Reserved isolation...

Страница 15: ...GND 100 Reserved isolation 99 Reserved isolation Table 2 2 AP483 Field I O Connector Pin Assignments 68 Pin Champ Carrier Connector 50 Pin Champ Carrier Connector2 Ribbon Carrier Connector1 Module P2...

Страница 16: ...ed isolation 35 Reserved isolation 10 10 19 38 Out2 44 35 20 37 Out3 40 Reserved isolation 39 Reserved isolation 11 11 21 42 Out4 45 36 22 41 DOut0 44 Reserved isolation 43 Reserved isolation 12 12 23...

Страница 17: ...5 Reserved isolation 20 20 39 78 Out6 54 45 40 77 Out6 80 Reserved isolation 79 Reserved isolation 21 21 41 82 In7_A 55 46 42 81 In7_A 84 Reserved isolation 83 Reserved isolation 22 22 43 86 In7_B 56...

Страница 18: ...7 Reserved isolation 3 3 5 10 In0_C 37 28 6 9 In0_C 12 Reserved isolation 11 Reserved isolation 4 4 7 14 Out0 38 29 8 13 Out0 16 Reserved isolation 15 Reserved isolation 5 5 9 18 In1_A 39 30 10 17 In...

Страница 19: ...8 39 28 53 In3_B 56 Reserved isolation 55 Reserved isolation 15 15 29 58 In3_C 49 40 30 57 In3_C 60 Reserved isolation 59 Reserved isolation 16 16 31 62 Out3 50 41 32 61 Out3 64 Reserved isolation 63...

Страница 20: ...eserved isolation 87 Reserved isolation 23 23 45 90 In5_C 57 48 46 89 In5_C 92 Reserved isolation 91 Reserved isolation 24 24 47 94 Out5 58 49 48 93 Out5 96 Reserved isolation 95 Reserved isolation 25...

Страница 21: ...d by multiple ground connections 2 6 Logic Interface Connector The AP module logic edge connector interfaces to the mating connector on the carrier board The pin assignments of this connector are stan...

Страница 22: ...IM_VPP 13 RECLK 14 UIM_RESET 11 REFCLK 12 UIM_CLK 9 GND 10 UIM_DATA 7 CLKREQ 8 UIM_PWR 5 TCK COEX2 1 6 1 5V 3 TMS COEX1 1 4 GND 1 N C WAKE 1 2 3 3V3 Note 1 The following mini PCIe signals are not used...

Страница 23: ...e system software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base...

Страница 24: ...CIe interrupt and I O registers The PCIe bus decodes 4K bytes for BAR0 for this memory space The memory space address map for the AP48X is shown in Table 3 2 Note that the base address for the board B...

Страница 25: ...ster2 0x0000 0034 31 0 Counter 0 Constant B Register 0x0000 0038 31 0 Counter 0 Constant B Register2 0x0000 003C 31 0 NOT USED 0x0000 0040 15 0 Counter 1 Control Register 0x0000 0044 15 0 Counter 1 In...

Страница 26: ...unter 4 Interrupt Information Register 0x0000 00A8 31 0 Counter 4 Read Back Register 0x0000 00AC 31 0 Counter 4 Constant A Register 0x0000 00B0 31 0 Counter 4 Constant A Register2 0x0000 00B4 31 0 Cou...

Страница 27: ...1 0 Counter 7 Constant A Register2 0x0000 0114 31 0 Counter 7 Constant B Register 0x0000 0118 31 0 Counter 7 Constant B Register2 0x0000 011C 31 0 NOT USED 0x0000 0120 15 0 Counter 8 Control Register...

Страница 28: ...upts The function of each of the interrupt register bits are described in Table 3 3 This register can be read or written with either 8 bit 16 bit or 32 bit data transfers A power up or system reset se...

Страница 29: ...ch to uniquely identify the system location of the carrier XXXXX System Slot identification bits are described by the AcroPack carrier card 31 to 8 Not Used Counters Interrupt Status Clear Register Re...

Страница 30: ...errupt Pending Clear 7 Counter Timer 7 Interrupt Pending Clear 8 Counter Timer 8 Interrupt Pending Clear 9 Counter Timer 9 Interrupt Pending Clear 10 31 Not Used Counter Interrupt Enable Disable Regis...

Страница 31: ...esponding trigger bit of this register will cause the counter function to be triggered Table 3 7 identifies the trigger bit location corresponding to each of the counters The contents of this register...

Страница 32: ...p 3 Counter 3 Stop 4 Counter 4 Stop 5 Counter 5 Stop 6 Counter 6 Stop 7 Counter 7 Stop 8 Counter 8 Stop 9 Counter 9 Stop 10 31 Not Used Load Read Back Register Write BAR0 0x0000 0018 This register is...

Страница 33: ...iting a 1 to the counter s corresponding toggle counter constants bit will cause the counter to use the values in Counter Constant A Register 2 and Counter Constant B Register 2 Writing a 0 will cause...

Страница 34: ...ality It defines the counter mode output polarity input polarity clock source and debounce enable The Counter Timer Module has ten 32 bit Counter Timers The Counter Control Register is cleared set to...

Страница 35: ...n X1 encoding decrement occurs on the falling edge of channel A when channel B leads channel A For X2 encoding two increments or decrements on each edge of channel A result from each cycle The counter...

Страница 36: ...implemented by software via the Load Read Back Register The quadrature measurement value can be read from the Counter Read Back Register Table 3 11 Counter Control Register Quadrature Position Measur...

Страница 37: ...e interrupt type must also be selected via bits 13 and 14 of the Counter Control Register The interrupt will remain pending until released by setting the required bit of the Counter Timer Interrupt St...

Страница 38: ...Off signal to stop and start the counter and thus the pulse width modulated output When InA is enabled via bits 5 and 4 of the control register for active low Gate Off input a logic low input will en...

Страница 39: ...is Disabled 10 Active HIGH In A 0 Counter is Disabled In A 1 Counter is Enabled 11 Disabled 7 6 InB Polarity External Clock Input 00 Disabled Default 01 External Clock Enabled 10 External Clock Enable...

Страница 40: ...be set to logic 110 to enable external InB clock input The timer can alternatively be clock enabled via an internal frequencies as selected via control register bits 12 11 and 10 InC can be used to e...

Страница 41: ...4 InA Polarity Counter Reload 00 Disabled Default 01 Active LOW In A 0 Counter Reinitialized In A 1 Inactive State 10 Active HIGH In A 0 Inactive State In A 1 Counter Reinitialized 11 Disabled 7 6 In...

Страница 42: ...bled for active high Gate Off operation a logic high will enable event counting while a logic low will stop event counting When InA is enabled for hardware load of Read Back Register an active high si...

Страница 43: ...has pullup resistor installed Bit 3 specifies the active output polarity when the output is driven Bit s FUNCTION 2 1 0 Specifies the Counter Mode 100 Event Counting 3 Output Polarity Output Pin ACTI...

Страница 44: ...s occurring at input InB of the counter are counted while the enable signal present on InA is active When the InA signal goes inactive the counter output will generate a 1 73 s output pulse and an opt...

Страница 45: ...3 Output Polarity Output Pin ACTIVE Level 0 Active LOW Default 1 1 Active HIGH 5 4 InA Polarity Enable Pulse of Known Width 00 Disabled Default 01 Active LOW Pulse 10 Active HIGH Pulse 11 Disabled 7 6...

Страница 46: ...pulse width measurement the pulse width being measured serves as an enable control for an up counter whose value can be read from the Counter Read Back Register When triggered the counter is reset an...

Страница 47: ...e is Measured 10 Active HIGH Pulse is Measured 11 Disabled 7 6 InB Polarity External Clock Input 00 Disabled Default 01 External Clock Enabled InB or Pin 49 10 External Clock Enabled InB or Pin 49 11...

Страница 48: ...at the beginning of the next active period The period being measured serves as an enable control for an up counter whose value can be read from the Counter Read Back Register When triggered the counte...

Страница 49: ...iod measurement 10 Active HIGH starts period measurement 11 Disabled 7 6 InB Polarity External Clock Input 00 Disabled Default 01 External Clock Enabled 10 External Clock Enabled 11 Disabled 9 8 InC P...

Страница 50: ...thus output When InA is enabled via bits 5 and 4 of the control register for active low Gate Off input a logic low input will enable the one shot counter while a logic high will stop the one shot cou...

Страница 51: ...utput Disabled 10 Active HIGH In A 0 Output Disabled In A 1 Output Enabled 11 Disabled 7 6 InB Polarity External Clock Input 00 Disabled Default 01 External Clock Enabled 10 External Clock Enabled 11...

Страница 52: ...bits not mentioned will remain at the default value logic low BIT FUNCTION 0 Counter equal to value in Counter Constant A Register available in Event Counting and Quadrature Position Measurement 1 Re...

Страница 53: ...counter s corresponding toggle counter constants bit will cause the counter to use the values in Counter Constant A Register 2 Writing a 0 will cause the counter to use the values in Counter Constant...

Страница 54: ...le 3 20 identifies the position of the available input bits Table 3 20 Digital Input Register Note that any registers bits not mentioned will remain at the default value logic low BIT FUNCTION 0 Din 0...

Страница 55: ...the ADC can be converted to temperature by using the following equation 15 273 1024 975 503 ADCcode C e Temperatur The 10 bits digitized and output from the ADC can be converted to voltage by using t...

Страница 56: ...0 95 1 0 1 05 Vccaux 1 71 1 8 1 89 Temperature operating range 40C 50 60C 100C Firmware Revision Register Read Only BAR0 0x0000 0200 This is a read only register The ASCII code representing the curre...

Страница 57: ...operation is considered Fail safe That is the Digital Input Output signals are always configured as input upon FPGA configuration during power up This is done for safety reasons to ensure reliable con...

Страница 58: ...Procedure CAUTION POWER MUST BE TURNED OFF BEFORE SERVICING BOARDS Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refer to the d...

Страница 59: ...r Temp Range I O Type 32 bit Counters AP482E LF1 2 40oC to 85oC TTL 10 AP483E LF1 2 40oC to 85oC TTL RS422 RS485 5 3 AP484E LF1 2 40oC to 85oC RS422 RS485 6 Summarized below are the expected current d...

Страница 60: ...to pass the following Vibration and Shock standards Vibration Sinusoidal Operating Designed to comply with IEC 60068 2 6 10 500Hz 5G 2 Hours axis Vibration Random Operating Designed to comply with IEC...

Страница 61: ...Hours MTBF Years Failure Rate FIT1 25 C 1 775 256 202 7 563 3 40 C 1 013 331 115 7 986 8 1 FIT is Failures in 109 hours 6 5 Counter Timers Counter Functions Quadrature Position Measurement Pulse Widt...

Страница 62: ...rical Characteristics 3 V Max Driver Common Mode Output Voltage 7V to 12V Common Mode Input Output Voltage Range Driver Differential Vout 1 5V Minimum RL 54 100mV Typical Input Hysteresis 96K Minimum...

Страница 63: ...tes with data payload of 4 Bytes for our typical AcroPack For each 4 Byte data sample 24 Bytes are sent 250 24 10 4 M samples sec or 41 6 M Bytes sec or 0 332 G bit sec Note 3 For our typical AcroPack...

Страница 64: ...SERIES AP48X ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 63 http www acromag com 63 https www acromag com Figure 1 AP482 Block Diagram Figure 2 AP483 Block Diagram...

Страница 65: ...SERIES AP48X ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 64 64 https www acromag com Figure 3 AP484 Block Diagram...

Страница 66: ...248 295 0310 65 http www acromag com 65 https www acromag com Appendix A AP CC 01 Heatsink Kit Installation This example will show how to install the AP CC 01 Heatsink kit with an APCe7020 carrier AP...

Страница 67: ...X ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 66 66 https www acromag com 1 Install two standoffs and secure with two screws 2 Install the AcroPack module 3 Install the Heatsink and secure wit...

Страница 68: ...P48X ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 67 http www acromag com 67 https www acromag com 4 AP CC 01 Installation is complete Note Make sure the thermal pad is making contact with the...

Страница 69: ...ower Down Type SRAM SDRAM etc Size User Modifiable Yes No Function Process to Sanitize Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when p...

Страница 70: ...2016 B LMP ARP Certificate of Volatility flash and OTP update Table 2 1 added 68 Pin Champ Carrier Connector and changed design to comply with to complies with for the EMC directives 13 APR 2017 C LM...

Отзывы:

Нет отзывов