Abov MC96F6332A, Руководство пользователя

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35
MC96F6432A
ABOV Semiconductor Co., Ltd.
7.12 UART0/1 Characteristics
(T
A
= -40°C ~ +85°C, VDD = 2.2V ~ 5.5V, f
XIN
= 8MHz)
Parameter Symbol MIN TYP MAX Unit
Serial port clock cycle time t
SCK
1800 t
CPU

16 2200
ns
Output data setup to clock rising edge t
S1
810 t
CPU

13
–
Clock rising edge to input data valid t
S2
– –
590
Output data hold after clock rising edge t
H1
t
CPU
– 50
t
CPU
–
Input data hold after clock rising edge t
H2
0
– –
Serial port clock High, Low level width t
HIGH
, t
LOW
720 t
CPU

8 1280
Table 7.12
UART0/1 Characteristics
t
HIGH
t
LOW
t
SCK
Figure 7.3 Waveform for UART0/1 Timing Characteristics
Shift Clock
Data Out D1 D2 D3 D4 D5 D6 D7 D0
Valid Data In Valid Valid Valid Valid Valid Valid Valid
t
SCK
t
S1
t
H1
t
H2
t
S2
Figure 7.4 Timing Waveform for the UART0/1 Module