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46 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts
Publication No. 500-9367855565-000 Rev. D.0
3
Channel 0 Clear Interrupt.
Writing a one (1) clears Channel 0 interrupts.
No
Yes/Clr
0
4
Channel 0 Inactive.
Reading a one (1) indicates a channel transfer is
complete.
Reading a zero (0) indicates a channel transfer is not
complete.
Yes
No
1
7:5
Reserved
Yes
No
000
Table 3-39 DMA Channel 0 PCI Dual Address Cycles Upper Address
DMADAC0: BAR0/1 Offset $B4
Bit
Description
Read
Write
Value after
PCI Reset
31:0
Upper 32 Bits of the PCI Dual Address Cycle PCI
Address during DMA Channel 0 Cycles.
If set to $0, the
DMA performs a 32-bit address DMA Channel 0
access.
Yes
Yes
$0
Table 3-40 PCI PIO Direct Slave Local Address Range
LAS1RR: BAR0/1 Offset $F0
Bit
Description
Read
Write
Value after PCI
Reset
0
Memory Space Indicator.
A zero (0)
indicates Local Address Space 1 maps into
PCI Memory space.
Yes
No
0
3:1
Reserved
Yes
No
$0
31:4
Range.
Specifies which PCI Address bits to
use for decoding a PCI access to Local
Address Space 1. Each bit corresponds to a
PCI Address bit. Bit 31 corresponds to
address bit 31. Write one (1) to all bits that
must be included in decode and zero (0) to
all others. (Used in conjunction with
PCIBAR3).
Yes
No
$FFE0000
(for 2 MBytes)
$FF00000
(for 16 MBytes)
$FC00000
(for 64 MBytes)
$F800000
(for 128 MBytes)
$F000000
(for 256 MBytes)
NOTE:
LAS1RR range must be power of 2. The LAS1RR range value is two’s complement of the range.
Table 3-41 PCI PIO Direct Slave Local Base Address (Remap)
LAS1BA: BAR0/1 Offset $F4
Bit
Description
Read
Write
Value after
PCI Reset
0
Local Address Space 1 Enable.
A one (1) enables
decoding of PCI addresses for PIO addresses for PIO
Direct Slave access to Local Address Space 1
(PCIBAR3).
Yes
No
1
3:1
Reserved
Yes
No
$0
Table 3-38 DMA Channel 0 Command/Status Register (Continued)
DMACSR0: BAR0/1 Offset $A8