UM031 FMC168/4/2
r1.7
UM031
page 9 of 28
FMC162 Single ended
FMC162 Differential
Font
Label
Input
FMC connector
signal names
Font
Label
Input
FMC connector
signal names
A
Input 1
st
A/D
CHA_*
A
Non-Inverted input 1
st
A/D
CHA_*
B
Inverted input 1
st
A/D
B
Input 2
nd
A/D
CHC_*
C
Non-Inverted input 2
nd
A/D
CHC_*
D
Inverted input 2
nd
A/D
Table 4: FMC162 Connector function assignment
4.2 Electrical specifications
The FMC168/4/2 card is designed to operate in LVDS mode. The connections on FMC bank
LA allow simultaneous sampling of eight (FMC168), four (FMC164), or two (FMC162)
channels. This is referred to as QDR LVDS mode. With the use of the connections on FMC
bank HA and HB, the digital interface rate can be reduced by a factor of two. This is referred
to as DDR LVDS mode.
4.2.1 QDR LVDS mode
In QDR LVDS mode each channel uses four LVDS pairs at 500MHz DDR, with a sampling
frequency of 250MHz. This mode can be used by both LPC and HPC carrier hardware.
4.2.2 DDR LVDS mode
In DDR LVDS mode each channel uses eight LVDS pairs at 250MHz DDR, with a sampling
frequency of 250MHz. This mode can only be used by HPC carrier hardware.
4.2.3 EEPROM
The FMC168/4/2 card carries a serial EEPROM (M24C02-WDW6) which is accessible from
the carrier card through the I
2
C bus. The EEPROM is powered by 3P3VAUX. The standby
current is only 0.01µA when SCL and SDA are kept at 3P3VAUX level. The EEPROM is
write-protected by default.
4.2.4 Stacked FMC
The FMC connector is referred as the top FMC connector as defined in ANSI/VITA 57.1. The
FMC168/4/2 can be used in a stacked environment when the bottom FMC connector is
mounted. The following connections are available between the top and bottom FMC
connector:
•
All gigabit data signals (DP[0..9]_M2C_P/N, DP[0..9]_C2M_P/N)
•
All gigabit reference clocks (GBTCLK[0..1]_M2C_P/N)
•
RES0
•
3P3VAUX, 3P3V, 12P0V, VADJ
•
JTAG (see section 4.2.3)
