UM031 FMC168/4/2
r1.7
UM031
page 10 of 28
4.2.5 JTAG
The FMC168/4/2 has a CPLD device in the JTAG chain. The TDO pin of the CPLD is
normally connected to the TDO pin of the top FMC connector through a buffer to ensure
continuity of the JTAG chain.
In a stacked environment, the TDO pin of the CPLD will be decoupled from the TDO pin of
the top FMC connector by the PRST_M2C_L signal coming from the bottom connector.
TRST#, TCK, TMS, and TDO are directly connected between top and bottom connector.
There is a build option to bypass the CPLD after factory programming for customers
requiring a direct connection between TDI and TDO on the top connector. Contact Abaco for
detailed information.
TDI
TDO
TDI
TDO
PRSNT_M2C_L
PRSNT_M2C_L
Top connector (to FMC carrier)
Bottom connector (to stacked FMC)
3P3V
OE
TMS
TMS
TCK
TCK
TRST#
TRST#
CPLD
Figure 5: JTAG connections
4.3 Main characteristics
Analog inputs
Number of channels
8 (FMC168)
4 (FMC164)
2 (FMC162)
Channel resolution
16-bit
Input voltage range
1Vp-p (4dBm) to 2Vp-p (10 dBm) programmable
Input gain
Programmable from -2dB to 6dB in 0.5dB steps
Input impedance
50Ω
Analog input bandwidth
500MHz (typical)
SNR (Fs = 250MHz)
SNR (Fin=11MHz): 70.643 dB (typical)
SNR (Fin=32MHz): 70.094 dB (typical)
SNR (Fin=64MHz): 66.576 dB (typical)
SNR (Fin=124MHz) 63.472 dB (typical)
SFDR (Fs = 250MHz)
SFDR (Fin=11MHz): 62.465 dBc (typical)
SFDR (Fin=32MHz): 67.082 dBc (typical)
SFDR (Fin=64MHz): 78.212 dBc (typical)
SFDR (Fin=124MHz) 72.499 dBc (typical)
External sampling clock input
Input Level
0dBm typical (LVTTL level supported)
