UM031 FMC168/4/2
r1.7
UM031
page 11 of 28
Input impedance
50Ω
Input bandwidth
4.5 MHz to 250 MHz. (AC coupled)
External reference clock input
Input Level
0dBm typical (LVTTL level supported)
Input impedance
50Ω
Input bandwidth
4.5 MHz to 250 MHz. (AC-coupled)
External reference clock output
Output Level
LVTLL/LVCMOS
External Trigger input
Format
LVTLL/LVCMOS (TTL compliant)
Threshold level 1.25V
Frequency range
Up to 125 MHz
ADC Output
Output data width
QDR LVDS mode; 4-pairs DDR per channel (LPC/HPC)
DDR LVDS mode; 8-pairs DDR per channel (HPC only)
Data Format
Offset binary or 2’s complement (programmable)
Sampling Frequency Range
250MHz internal clock
Up to 250MHz external clock
Table 5 : FMC168/4/2 daughter card main characteristics
4.4 Analog input channels
The analog input signals are connected to the FMC168/4/2 via SSMC connectors on the
front panel. Each channel can be assembled as an AC-coupled or DC-coupled input.
Optionally, the FMC164/2 supports differential inputs using two connectors per channel. A
125MHz low-pass input filter can be assembled.. The filter option needs to be specified at the
time of ordering. See Chapter 9 Ordering information for details.
DC
Coupling
LPF
ADC
AC
Coupling
IN
Filter Bypass
Figure 6: Analog input block diagram
4.4.1 AC coupling
The AC-coupled input option uses wideband RF transformers (TC4-1W, 3-800MHz). Two
transformers are used head-to-head to compensate for imbalance and reduce harmonic
distortion. The input impedance is matched to 50
Ω
.
4.4.2 DC coupling
The DC-coupled input option uses Analog Devices ADA4939-1 ADC driver. The gain (G) is
set to one giving maximum input bandwidth (BW). To reduce harmonic distortion in DC-
