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UM031 FMC168/4/2 r1.7
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4.8.2 PLL design
The PLL functionality of the AD9517 is used to operate from an internal sampling clock. The
VCO is a high-performance oscillator (CLV1225A-LF). As a build option, the internal VCO of
the AD9517 can be enabled. Contact Abaco for details.
The default loop filter is designed for a phase detector frequency of 10MHz, loop bandwidth
of 10kHz, phase margin of 45 deg, and a charge pump of 4.8mA.
Figure 9: VCO loop filter design
4.9 Power supply
Power is supplied to the FMC168/4/2 card through the FMC connector. The pin current rating
is 2.7A, but the overall maximum is limited according to Table 6.
Voltage # Pins Max Amps Max Watt
+3.3V 4 3 A 10 W
+12V 2 1 A 12 W
VADJ (+1.8V / +2.5V) 4 4 A 10 W
VIO_B (VADJ) 2 1.15 A 2.3 W
Table 6: FMC standard power specification
The power provided by the carrier card can be very noisy. Special care is taken with the
power supply generation on the FMC168/4/2 card to minimize the effect of power supply
noise on clock generation and data conversion. However, properly filtered power supplies
from the FMC carrier are recommended.
Table 7 shows typical currents per power rail. VIO_B is connected to VADJ on the
FMC168/4/2. Current drawn from VADJ by the FMC168/4/2 is minimal. The typical power
consumption is 13.5W.
Power plane Typical Maximum
VADJ I
VIO_B, typ
I
VIO_B, max
3P3V 1344mA
12P0V 750mA
3P3VAUX (Operating)
3P3VAUX (Standby) 0.1 mA
0.01 µA
3 mA
1 µA
Table 7: Typical / Maximum current drawn from FMC carrier card
5 Controlling the FMC168/4/2
Good knowledge of the internal structure and communication protocol of relevant onboard
devices is required for controlling the FMC168/4/2. Please refer to the datasheets mentioned
R1
51.0
C2
1.00uF
C1
68.0nF
R2
100
C3
33.0nF
Ct
0F
VCO
CLV1225A