Aaeon SBC-657, Руководство пользователя

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Chapter 3 Award BIOS Setup 47
3.7 Advanced Chipset Features
Figure 3.4 Advanced Chipset Features
3.7.1 DRAM Timing By SPD
This item allows you to select the value in this field, depending
on whether the board has paged DRAMs or EDO (extended data
output) DRAMs.
The choices: Enabled(Default), Disabled.
3.7.2 DRAM Clock
This item allows you to control the DRAM speed.
The choice: Host Clock, HCLK-33M, HCLK+33M
3.7.3 SDRAM Cycle Length
This field sets the CAS latency timing.
The choices: 3, 2