UM008 FMC204 User Manual
r1.14
UM008
- 9 -
# Pairs
# Clock pairs
# Data pairs
LVDS Clock
1
1
LVDS Trigger
1
1
LVDS Sync
1
1
DAC #1
18
LVDS Clock
1
LVDS Sync
1
LVDS Data
16
DAC #2
17
LVDS Clock
1
LVDS Sync
0
LVDS Data
16
2.5V or VADJ Level I/O
routed to CPLD (see board
revision)
0
4
# Total pairs
3
39
Table 3: HPC signal usage
1
1
Signal CLK3_BIDIR_P/N is not connected.
