UM008 FMC204 User Manual
r1.14
UM008
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2
General description
The FMC204 is a quad-channel D/A FMC. The FMC204 provides four 16-bit D\A channels
that enable simultaneous sampling at a maximum rate of 1 Gsps. The sample clock can be
supplied externally through a coax connection or by an internal clock source (optionally
locked to an external reference). A trigger input for customized sampling control is also
available.
The FMC204 daughter card is mechanically and electrically compliant to the FMC standard
(ANSI/VITA 57.1). The card has a high-pin count (HPC) connector, front panel I/O, and can
be used in a conduction-cooled or conventional air-cooled environment.
The FMC204 allows flexible control of clock source, sampling frequency, and calibration
through a SPI communication bus. The FMC204 card is equipped with power supply and
temperature monitoring with several power-down modes to switch off unused functions to
reduce system level power and heat. The FMC204 is well-suited for software defined radio
(SDR), battery, or other low power source applications. It is ideal for airborne applications
where power demand affects mission range and on-station mission time.
DAC A
F
M
C
H
ig
h
-p
in
C
o
u
n
t 4
0
0
-p
in
s
L
V
D
S
Board
Monitoring
LVDS Clock [1]
Clock / Sync
Tree
DAC B
D/A: DAC5682Z
16-bit @ 1 Gsps
DAC C
DAC D
LVDS Data [16]
LVDS Clock [1]
LVDS Data [16]
Board
Control
I
2
C
D/A: DAC5682Z
16-bit @ 1 Gsps
Clock /
Reference
Trigger /
Sync
EEPROM
x
1
/
x
2
x
1
/
x
2
LVDS Clock [1]
MGT [4]
LVDS Trigger [1]
Tx [5]
M
IC
T
O
R
3
8
-p
in
s
M
u
lt
i G
ig
a
b
it
T
ra
n
s
c
e
iv
e
r
(o
p
tio
n
a
l o
n
r
e
v
is
io
n
1
)
M
IC
T
O
R
3
8
-p
in
s
M
u
lt
i G
ig
a
b
it
T
ra
n
s
c
e
iv
e
r
(o
p
tio
n
a
l o
n
r
e
v
is
io
n
1
)
H
D
M
I
LVTTL [4]
Status & Control
LVDS Sync [1]
1:2
Rx [5]
Tx [5]
Rx [5]
2.5V / Vadj level single
ended [4]
Figure 1: FMC204 block diagram
