Nabu 1100 System Technical Manual Download

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Summary of Contents for 1100 System

Page 1: ... The NABU 1100 System A Technical Guide ...

Page 2: ...produced with the permission of the manufacturers involved Intel Corporation NEC Information Systems Inc NEC Microcomputers Volker Craig ltd Western Digital and ZiJog Inc Because of our policy of constantly searching for ways to improve our products all specifications are subject to change without notice ...

Page 3: ...TORY 1 INTRODUCTION 2 SYSTEM MAINTENANCE 3 THE COMPUTER Manufactured by Nabu Corporation 4 THE KEYBOARD TERMINAL Manufactured by Volker Craig Limited 5 THE PRINTER Manufactured by NEe Information Systems Inc ...

Page 4: ... well the system provides interfaces for printer and controls The keyboard terminal is manufactured by Volker Craig and is microprocessor based providing a full set of standard functions as well as a variety of options The non glare screen can display up to 24 lines x 80 characters a total of 1920 character positions The keyboard is detachable and features a full set of punctuation and special sym...

Page 5: ...d service Technician Regular cleaning should be done by the operator at least once a month as follows vacuum under the system cabinet vacuum paper dust out of printer clean cabinet printer and screen with any spray cleaner and a soft cloth NOTE Spray the cleaner only on the cloth NOT ON THE EQUIPMENT The system cabinet has been installed with rollers for maneuverability when cleaning etc However i...

Page 6: ...The Computer Manufactured by Nabu Corporation ...

Page 7: ...Diagram of Dynamic Memory Board FIGURE 5 Dynamic Memory Board Layout 3 0 INPUT OUTPUT BOARD General Information Specific Features Input Output Board Parts List FIGURE 6 Schematic Diagram of Input Output Board FIGURE 7 Input Output Board Optional Circuit 1 FIGURE 8 Input Output Board Optional Circuit 2 FIGURE 9 Input Output Board Power Supply FIGURE 10 Input Output Board Layout 4 0 FLOPPY DISK DRIV...

Page 8: ...ement a real time clock for the system The computer hardware is located in the upper drawer of the specially designed cabinet Directly against the right side of the drawer as you open it are the Disk Drives manufactured by Shugart They feature low heat dissipation improved access time capacity for single or double density recording on standard diskettes and write protection and programmable door l...

Page 9: ...ot implemented Not implemented Not implemented Not implemented Implemented but not used Not implemented Not implemented Not implemented Not implemented Not implemented Disables the 8 status signals Disables the 5 control output signals Ground not implemented Not to be defined Disables the 16 address signals Disables the 8 data output signals Master tim1ng signal status valid strobe Hold control si...

Page 10: ...ted Not implemented Not implemented Not implemented Memory request Memory refresh Enables phantom slaves Memory write Reserved for future use Ground not implemented Reserved for future use Ready input Primary interrupt request HOLD control signal Resets bus master devices Control signal identitying BSl Data bus control signal Data in control signal Address bit 0 Address bit 1 Address bit 2 Address...

Page 11: ...SITIONS IN 1 Empty 2 FLOPPY DISK CONTROLLER BOARD 3 INPUT OUTPUT BOARD 4 Empty 5 CPU BOARD 6 Empty 7 MEMORY BOARD 8 Empty NOTE Positions indicated are numbered from left to r1ght as viewed from the front of the cabinet ...

Page 12: ... 5 and 24 volts for the disk drives It consists of four major components transformer rectifiers filter capacitors and regulators The transformer primary has two llOV windings They are connected in parallel for use with a llOV supply and in series for use with a 220V supply SPECIFICATIONS INPUT OUTPUT 110 Volts AC 60 Hz single phase Unregulated 8 Volts 14A 16 Volts 3A 16 Volts 3A RegUlated 5 Volts ...

Page 13: ...s memory block can be set using on board jumpers The board also performs an automatic jump to a user selected memory address on system start up or reset The clock frequency of the main processor is also selectable between 2 and 4 MHz When the 4 MHz clock frequency is used the board automatically inserts one wait state when the on board EPROM or RAM is accessed When used in the Nabu 1100 computer s...

Page 14: ...ower is turned on or a reset signal is received the CPU jumps to one of two hundred and fifty six possible memory locations The jump address is selected by the eight address jumpers JP 9 to JP 16 Only the eight most significant address bits A15 A8 are used to decode the jump address The eight least significant address bits A7 AO are taken as logic 0 as shown on the next page Power On Jump Address ...

Page 15: ...ck is set by jumpers JP l through Jp 3 The three most significant address bits are used to set the address of the block Table 1 on the following page lists the possible base addressses of the block corresponding to each jumper connection JUMPERS JP STARTING ADDRESS IN HEX OF ROM 2 ROM 3 RAM l RAM 2 ROM 1 0800 1000 1800 ICOO 2800 3000 3800 3eOO 4800 5000 5800 seoo 6800 7000 7800 7eOO 8800 9000 9800...

Page 16: ... L connected to enable ROM 1 RAMls connected to enable ROM 3 connected to enable ROM 2 In addition enabling on board RAM s and EPROMls renders any external devices or memory at the selected address blocK inaccessible to a read instruction However I a wr i te operation will write into all devices located there The standard Nabu ACP lIOI is shipped with the following memory setting Jumpers JP 1 2 3 ...

Page 17: ...ically require a refresh to maintain the data stored within the memory cell The Nabu CPU board brings the memory refresh signal from the Zilog Z 80A microprocessor to the S 100 bus Pin 66 on the 8 100 bus is designated by Nabu as the memory refresh signal RF8H The memory request signal from the Z 80A processor is also brought out to the 8 100 bus Pin 65 named as MREQ is used to indicate a valid me...

Page 18: ...state outputs Quadruple D type flip flop Dual retriggerable monostable multivibrator with clear Dual D type rising edge triggered flip flop with preset and clear Quadruple 2 input NAND with Schmitt triggered inputs Hex inverter Quadruple 2 input AND Quadruple 2 input OR Central processing unit 4 MHz Quadruple 2 line to l line multiplexer Quadruple 2 input NOR Hex non inverting bus driver Hex inver...

Page 19: ... 6 1 10 k f 1 k J L 100J 220 J 22 1l 100 kA 9 resistor pack of 1 k resistors with common pin 1 8 000 MHz parallel resonant Descriptioo 14 pin socket 16 pin socket 18 pin socket 20 pin socket 24 pin socket 40 pin socket Delta 680 0 5 220 Heatsink 6 32 x 3 8 machine screw 6 32 nuts p c board ...

Page 20: ...pages have been reproduced by perm1ssion of Zilog Inc 1979 80 81 This material shall not be reproduced without the written consent of Zilog Inc Z 80A is a trademark of Zilog Inc with whom the publisher is not associated ...

Page 21: ...implemen tation of a pnority interrupt scheme Little if any additional logic is required for daisy chaining Duplicate sets of both general purpose and flag registers are prOVided easing the design and operation of system soft ware through smgle context switching background foreground programming and single level interrupt processing In addi tion two l6 bit index registers faCilitate proqram proces...

Page 22: ...or alternate registers accessible to the programmer The dternate set allows oppratlOn in foreground background mode or it may be reserved lor very tast interrupt response The Z80 also contains a Stack Pointer Pro gram Coun er two mdex registers a Refresh register counter and an Interrupt register The CPU 15 easy to incorporate mto d system smce j requires only l single 5 V power source all output ...

Page 23: ...ct Memory Access con troller provides dual port data transfer operations and the ability to terminate data transfer as a result of a pattern match The SIO Serial Input Output controller offers two channels It is capable of operating in a variety of programmable modes for both synchronous and asyn chronous communication including Bi Synch and SDLC The DART Dual Asynchronous Receiver Tr lnsmitler de...

Page 24: ...U Reglater Size BitB Register A A Accumulator 8 Continued F F Fl gs 8 B B General Purpose 8 C C General PurposA 8 D 0 General Purpose 8 E E General PurposlO 8 H H General Purpose 8 L L General Purpo 8 Table I zeo CPU Regl tel1l Interrupts General Operation The CPU accepts two interrupt mput signals NMI and INT The NMI is a nonmaskable interrupt and has the highest pnorHy INT is a lower priority in...

Page 25: ...he data bus during the interrupt acknowledge cycle The high order byte of the interrupt service rouflne address is supplied by the 1 Interrupt register This flex ibility in selecting the interrupt service routine address allows the peripheral device to use several different types of service routines These routines may be located at any avatlable location in memory Since the interrupting device sup...

Page 26: ...put output devices These addressing modes include l Immediate l ImmedIate extended l Modifted page zero Relative u Extended LJ Indexed fl Register IJ Register indirect lJ Implied r Bit 8 Bit Symbollc nGi Opcod Ko ol Ko ol M Ko ol T Load MlDeaoDJ t OlM ratioD 5 Z H PIV II C 18 5 3 210 a BY eyel SloI eo JQ lJtl Group LD r l r X 01 LD r n X 00 110 OCI J B 001 C LD L HL HLJ X X 01 c 110 7 010 D LD c I...

Page 27: ... jJ 011 101 DD 15 II AF ISP II XH I 00 01 E5 SP SP 2 PUStilY ISP 21 lYL X X 11 III 101 FD 15 ISP I IYH 11 100 101 5 SP SP 2 POPq qqH SP 1I X X 11 qqO 001 10 qqL SP SP SP 2 POP IX lXH ISP I X X 11 011 101 DO 14 IXL IS II 100 001 EJ SP SP 2 pop If IYH SP X X 11 III lOJ FD 14 IYl SPI II 100001 EI SP SP 2 NOTES dd lA ny nl the reql r l lIH Be DE HL SP qq B H ll o the rtliJjs cr pa Lr AF BC DE HL P _I ...

Page 28: ...1 Be r l hpfw Se p e Q 7 iil tql A HL l1t erw l Z I Bit ADDA r A A r X X V I r He Arithmetic ADDA A A n X X V 111QQ I11G 000 B and Logical 001 c 010 D Group ADD A lHLI A A IHU X X V III QQQ 110 011 E ADD A IX d A A t IX ri X X of I OJ J 1 1 DO 9 00 H Om llO 101 L J III A ADD A OY d A A OY d X X V 11i IOJ fD 9 O Q 110 d APe A A A TCY X X V Il f lS dOY 01 t n SUB s A A s X X v mll WLJ IX dJ Oy dl IS...

Page 29: ... JJ tl _B C t Arithmetic 00 BC ADC HL HL H i ss CY I I J 1 En 15 01 DE Group 0J 10 HL SP SHe HL HI Hi C1 V I EiJ 15 A D iX c pp IX IX p IS I X Be OJ DE 10 IX II SP ADD IY C IY Y X X II 1 fl 15 rr Reg r oo llc OJ DE Ie IY Ii SP c S i X IY d HI J IX x X X 0 I DO iG 0 l JD 01 13 l C IY IY _ IY X X L 1 I D 10 lie 10 c 23 J C I X X JQ so j 6 DEC IX IX IX I X X il JC11 fD lQ 00 01 1 B DEelY IY x X II 11...

Page 30: ...up sn b ilX dJ JlX dJb SET h r SET b HLI b HUb I x x li ilGI jil CB IT b 01 011 CB IT 0 iIn I iJ IU l J II DOl 01 CR d 15 23 SET b tlY to dl lY d1b j x b 11l JI WI HJ II rill ca 2 1 J RES D m mb 0 m T HLL JlX dl IV di X To torm ne orl opcode rl pl ce ill 01 SET b wi h ill Fldq9 and tIme llotate lor SET nslrl lclL n r l JI1e PC PC t IR C e IIC O contmllF IIC PC PC t 1 NC I I C L Qrltlnuo He o PC Pe...

Page 31: ... I III Jl boA SP 2l PCl PCH O 001 H PCl P 010 IOH 011 ISH 100 20H 101 28H 110 3DH III 381l NOH RErN I d IFF IfF 1 Input aDd IN A nl A 01 X X Ii Oll 011 DB II 010 AO A7 Output Group n Ace 10 AS AIS IlI CI IC X X P 11 101 101 ED 2 3 12 GloAo A7 il r lJO only Ih 01 r 000 BtoAs AI5 f1aq fl win be affected CD INI Hl lCI X X X X X 11 101 101 ED IS C io Ao A7 II B 1 LO 100 010 A2 B 0 AS AIS HL ilL INIfI ...

Page 32: ...g S 1 il the MSB of the resul s I Zero flag Z 1 if the result of the operatIOn 1 O Parity or overflow flag Panty P and overHow V share the same UaG Logical operatwns affect this lag WIth the panty at the resl1l1 while arithmetic operatIOns aflee thIS fldg with Ihe overflow of the result II P V hoids pdnly PIV 1 If the result of the operaiion is even P V 0 if result is odd l P V holds overflow PIV ...

Page 33: ...ite operation IORQ is also generated concurrently with Ml during an interrupt acknowledge cycle to indi cate that an interrupt response vector can be placed on the data bus Machine CycJe One output active Low Ml together with MREQ indicates that the curren machine cycle is the opcode fetch cycle instruction execution MI together with IORQ indicates an interrupt acknowledge cycle MREQ Memory Reques...

Page 34: ...ram Counter PC m the address hus at the s ari of ihe Ie F qu e _ Approximately onrhalf r led 1 2 _ MREQ goes actlVA Th fidlmq pdq of Iv1RFQ can be used directly dS d tllE Er dhl o rd mic memories When iJctlv HD lndlCd e thell the memory dati Cfm be onabled In the CTU dnln bus Thp CPU samples thp WATT input with Ih liSlT n dqe Jt dock sldte T L Dunn clock SUi les T3 And T4 of an M 1 yele dynarmc HA...

Page 35: ...ycle MREQ also becomes active when the address bus is stable so that it can be used directly as a Chip Enable for dynamic memories The WR line is active when the data bus is stable so that it can be used directly as an R W pulse to most semIconductor memories T I l jD D v WAIT 1 _ _ __ lI _ _ _ l AD O IE A DO D l 1 W W TIE 1 i __ __ I O IE ATIO _ Do D7 1 r DA TA OU T T CLOCK Figure 6 Memory Read o...

Page 36: ...ycle The CPU samples the interrupt signal with the ris mg edge of the last clock cycle at the end of any instruction Figure 8 When an interrupt is accepted a special Ml cycle is generated During this M l cycle 10RQ becomes active instead of MFfEQ to indicate that the inter rupting device can place an 8 bit vector on the data bus The CPU automatically adds two Wait states to thIS cycle CLOCK NT WAi...

Page 37: ...rjq cdqe mus Cl UI Hl He tn iht n ir q edQ i the dOl k cycle pret m 1Jnq TLAST figure 9 Non Maskttble Interrupt Request Operation BUB Request Acknowledge Cycle The CPU sllmples BUSREQ with the rising edge of the last clock period of any machine cycle Figure 10 If BUSREQ is aelive the CPU sets Its address data and MREO lOllQ RD and WR lmes to a high impedance slate with the riSing edge of the next ...

Page 38: ...Acknowledge Cycle ReBet Cyele RESET must be active for at least three clock cycles for the CPU to properly accept it As long as RESET remains active the address and data buses float and the control outputs are inactive Once RESET goes CLOCK in JI inactive two internal T cycles dre consumed before the CPU resumes normal processing operation RESET clears the PC register so the first opcode fetch wil...

Page 39: ...ime after Clock 1 0 0 0 19 TdCr Mlf Clock I to MI I Delay 130 100 80 20 TdCr Mlr Clock t to MI Delay 130 100 80 21 TdCr RFSHf Clock t to RFSH 1 Delay 180 130 110 22 TdCr RFSHr Clock t to RFSH t Delay 150 120 100 23 TdCf RDr Clock 1 to RD t Delay 110 85 70 24 TdCr RDf Clock 1 to RD I Delay 100 85 70 2S TsD Cf Data Setup to Clock j during 60 50 40 M2 M3 or Ms Cycles 26 TdA IORQf Address Stable prior...

Page 40: ... RO I Delay 53 Number Symbol _ _ _ _ _ _ AC Charac teristics Conlmued FC lr J lef pe c ds t r h i T n O t r c rl 1r if dlCl dte rVHdlTJ k s JS q h _ J _ l tfC va ups CibcNI 1 S dlTled Tr iF nc Footnote to AC Characteristics Number Symbol zeD Z80A _ _ _ zaoe I 2 TcC TwCh Twe TwC Ire t TlC AlthoLqh stilti by desI9fl TwCh of qr dter a 2U J p s b not qUdrlH f d lweI TwC I TrC TIC Althouqh talle hy dp ...

Page 41: ... S Vee S 5 25 V 55 C to 125 C 4 5 V S Vee S 5 5 V Standard Test Condition DC Character I tics Symbol VIIC V1HC V 1L V1H VOL VOH Icc Parameter Clock Input Low Voltage Clock Input High VoltagE Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current 280 280A 280B Input Leakage Current 3 State Output Leakage Current In Float All ae parameters assume a load capa...

Page 42: ...840DB CE 6 0 MHz 280B CPU 40 pin 28400 DS 2 5 MHz Same dS above ZB400B CM 6 0 MHz Same as above 28400 PE 2 5 MHz Sa me as above 2840GB CMB 6 0 MHz Same as above 28400 PS 2 5 MHz St lnle a bov 28400B CS 6 0 MHz Same as above 28400A CE 4 0 MHz 280P CPU 40 plIl 13400B DE 6 D MHz Same as above 28400A eM 4 0 MHz fi JTW as above 73400B DS n O MHz SarnA as above ZS400A CMB 4 0 MHz Same as iibove 28400B P...

Page 43: ...oard ofters a full 64K bytes of read write memory however only 62K bytes are available to the user in the Nabu 1100 System since 2K bytes are allocated to the diSK bootstrap program in ROM A signal called PHANTOM from the 8 100 bus can be utilized to allow user ROM to overlay the RAM In the Nabu 1100 System the access time of the memory chips is 150 nanoseconds ns permitting operation at 4 MHz wlt...

Page 44: ...BFFFH Jp 4 4 RAM 25 RAM 32 COOUR FFFFH Each bank is enabled by installing the appropriate jumper MemQry Refresh As mentioned the memory refresh is done automatically by the Z 80A CPU through the 8 100 bus The CPU contains a 7 bit memory refresh counter which is incremented automatically after each instruction fetch The data in the counter is sent out on the lower portion of the address bus along w...

Page 45: ...out lines of the memory chips are buffered by U9 and U14 The data in lines are always enabled and the data out lines are controlled by US whose four inputs are conditioned by PDBIN SMEMR MREQ PHANTOM and by two high address bits AlS and A14 Reading of the RAM contents is not allowed when US is disabled however writing into the RAM is still permissible PHANTOM is normally pUlled high through a resi...

Page 46: ...chottky multiplexer Octal buffer line driver witn 3 state outputs Hex inverter with Schmitt triggered inputs TTL compatible logic delay module 5 V positive voltage regulator 12 V positive voltage regulator 16384 bit dynamic RAM 150 ns 5 1 V 1 0 W 5 zener diode CI C4 CI3 C5 CI2 C14 C59 Resistors RI RN1 RN2 RN3 Quantity 36 9 2 2 2 2 1 10 F 25 V tantalum electrolytic 0 1 F 680ll I 0 5 W 10 5 resistor...

Page 47: ... 05 00BUS 1 IIlN2 J 1 1 T I rCS CI2 CI4 C59 RASr1J RAS 1 RAS2 4 RAS3 6 Vss 41 16 15 RN2 2 nN2 1 I RAM RAM3 2 1 CAS nN I RN2 33 nN3 3 3K n1 68 Cl C4 CI3 If C 5 C 12 C 14 C 5 5 r1J l VCC I L l wn liE A1 3 nN3 S 13 A2 2 nN3 4 2 1 12 A3U2 nN3 3 4 2 U5 15 Afl r1J nN3 2 5 8 V OD 12 v VI 01 QiL 14 SEE TABLE FOR RESISTons AND CAPAC liORS VAL UES 4 fj Vee 5 v A vBS S v S JP IS A JUMPEn WIRE lr1J av pWRI77 ...

Page 48: ... w w w c 14 S 81 3 81 1 sGI 9 4eg n n n oC lo 14 6 gI 4 SgI 2 sf I o sgQ o n n n n otrr o ro o ro o ro U1 14 7 9I s gI 3 81 1 f6 eG n 0 0 n on U1 U1 U1 U 1 U1 01 4 8 s9I 6 gI 4 S gI 2 7 gQ BANK BANK a BANK BANK 1 2 tJ 3 t JOo 4 I a 8 o tl _ _ 0 0 81 7 S7 8 n o g D1 R1 IS601 I I C16 Cl 780S 10uF L C2 10uF o O l g 0 g ON l il I g o 9 D VlO lw 1 ANDICOM CORPORATION I I I LE 6 41 DYNAMIC MEMO R Y BOA ...

Page 49: ...ncritical clock timing requirements allow use of the multiplexing techniaue while maintaining high performance FEATU RES 16384 Words x 1 Bit Organ zation High Memory Density 16 Pin Ceramic and Plastic Packages Multiplexed Address Inputs Standard Power Supplies 12V 5V 5V Low Power DiSSipation 462 mW Active MAX 40 mW Standby MAXl Output Data Controlled by CAS and Unlatched at End of Cycle Read Modif...

Page 50: ... 2 Relative to Vss COMMENT Stress above those listed under Absolute Maximum tings may cause permanent damage to the dwice This Is a nress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended Periods may affect device relia...

Page 51: ...20 0 M sel up lime IWCS CAS to WRITE 0 80 del y CWO RAS 10 WRITE 2 0 00 60 20 20 delly IAWO No_ D AC m_ureme u an me IT 5 I VIHC Iml 0 VIH mi iII d Vlllmex are ele e ce level 10 mnsu i g t m g of npul s gnal Aho I nsit o lime are eill ured betwee VIHC 0 VIH arid Vll Q The spKil catlo lor IRC minI end RWC Iml are ullld only 10 dicate cycle time al hich p ope ope ation OVe Ihe fuJilempe atu e III CO...

Page 52: ...Dour H gh Current Impedance Refresh Vaa RAS cycling 1883 200 A m VIHC Current tRC 375 ns Page Mode Vaa RAS VIL CAS 1884 200 A cycling Current tpc 225 ns Vaa 5V OV Input Leakage IllL 10 10 A VIN 7V any inputl all other pins not under test OV Output Leakage lOlL 10 10 A DOUT is disabled OV VOUT 0 5 SV Output High Voltage VOH 2 4 V lOUT S mA Logic 1 Output Low Voltage VOL 0 4 V lOUT 4 2 mA Logic 0 DC...

Page 53: ...ion at extended frequencies o 1 0 2 0 3 0 4 0 CYCLE RATE MHz 103 tRC ns FIGURE 2 o lOrnA 20 rnA 30mA 40mA 50 mA i I 2 w a a u it o a x 4 0 3 0 2 0 CYCLE TIME RC In l 320 500 40 1375 pOO 250 1 0 I 50 1 11 o i w z w iii CYCLE RATE MHz 103 t RC lnsl FIGURE 3 Maximum 003 versus cycle rate for device oPeration 8t extended frequencies CYCLE TIME tAC ns 320 1000 I 500 400 300 250 375 pJJ5 SPEC LIMIT O I ...

Page 54: ...AS i I t IAR 1 ADDRESSES WRITE V IHC _ V L _ OH VALID GOUT OPEN DATA vOL _ WAITE CYCLE ec V He V L_ V HC _ CAS V L_ ADDR ESSES V H_ V 1L _ _ OPEN _ READ WAITE AEAD MODIFY WRITE CYCLE OFF Vl _ __ w j u o _ DATA V He e e CAS V ADORESSfS WRIT He 0 D aUl m 0 ...

Page 55: ...NLY REFRESH CYCLE l ADDRESS _ _ _ _ _ _ _ _ _ _ _ _ DPEN _ Note CAS V HC WRITE Don e e PAGE MODE READ CYCLE A AS V 1HC v V HC CA v v ADDRESSES v lL DOUT vO V O WRITE V HC v PAGE MODE WRITE CYCLE V HC v W V1HC v v ADDRESSES v WRITE V 1HC _ 0 RAS _ 1 ...

Page 56: ...ill remain in the high impedance state throughout the cycle For a READ WRITE OR READ MODiFY WRITE cycle the data output will contain the data in the selected cell after the access time Data out will assume the high impedance state anytime that CAS goes high The page mode feature allows the IlPD4 16 to be read or written at multiple column PAGE MODE addresses for the same row address This is accomp...

Page 57: ... 70 F 3 0 051 G 2 54 MIN O 10MtN H O 5MIN 0 02 MIN r i 4 0S M AX 0 16 MAX J 4 55 MAX 0 18 MAX K 7 62 0 30 L 0 25 0 10 M 0 25 0 01 0 05 11 A L IJ r r _e _FU_ i l j lPD416D Ceramic ITEM MILLIMETERS INCHES A 20 5 MAX 0 81 MAX B 1 3e 0 05 c 2 54 0 10 D 0 0 02 E 17 78 0 70 F 1 3 0 051 G 15MIN 0 14 MIN H a 5M N 0 02 MIN I 4 6 MAX 0 18 MAX J 5 1 MAX 0 20 MAX K 7 0 30 L 7 3 2 M 0 27 0 01 ...

Page 58: ...allel output port is a simple 8 bit D type latch7 which can be easily programmed to interface with any parallel printer The six programmable counters are implemented by two 8253 programmable interval timers PIT s Two of the six counters are configured as baud rate generators for the two serial ports while the remaining four counters may be used as desired by the user eg rate generators real time c...

Page 59: ...e system which is normally a NEC Spinwriter The associated PCI U3 is programmed the same way as U6 the only exception being the baud rate is 1200 By connecting the reverse channel signal from the NEC printer to CTS of U3 no communication protocol is needed However if an 8251A is used in U3 a problem of repeating characters will occur whenever the reverse channel becomes active This problem can be ...

Page 60: ...r in order for data transmission the resistor Rl must be present to make CTS active Jumpers Jp 5 through JP 8 on pins 6 5 4 and 20 respectively on connector Jl are factory installed for interfacing to the NEC Spinwriter Parallel Ports One parallel output port is available from J3 to the user and is normally used to interface to a parallel printer if needed It is assigned the address 8DH in the Nab...

Page 61: ...y are available to the user through wirewrapping for implementing a real time clock which will be discussed in the next section The address assignments for the timer are as follows Counter Address Function U20 o 1 2 Control register 84H 1 85H 86H 87H Available to the user Ul8 o 1 2 Control register 88H 89H 8AH 8BH Clock for List PCI Clock for console PCI For the timers used as baud rate generators...

Page 62: ...ot used in the input output scheme for the Nabu 1100 system However the board is preset to enable interrupts with the interrupt vector set to 10H for future expansion to a multi user system Thus the standard board is shipped with interrupt jumpers installed as shown 0 0 A7 0 0 A6 0 0 AS o 0A4 0 0 A3 0 0 A2 0 0 Al 0 0 EI NOTES 1 Interrupt vector setting without jumper means logic one 2 AO is always...

Page 63: ...a 1 Hz clock 1 second period Counters 2 and 3 are used to accumulate the count The counter contents can then be read by the CPU to determine the time By connecting the timer s output to the Interrupt Request pin of the CPU the timer can be programmed to interrupt the CPU at a preset time Detailed instructions on the conf guration of the 8253 PIT are provided in the manufacturer s data sheets ...

Page 64: ...ace improved version Octal buffer line driver witn 3 state outputs Quadruple 2 input positive NAND buffer with open collector outputs Octal D type flip flop Quadruple 2 input NAND Hex inverter Intel programmable interval timer Hex bus driver Quadruple 2 input OR Quad exclusive OR witn open collector outputs Dual 2 to 4 line decoder demulti plexer Triple 3 input NAND Dual D type positive edge trigg...

Page 65: ...Quantity 1 1 3 4 6 6 1 Description delta 1 630 0 50 dual TQ 220 heats ink 4 position dip switch 26 pin right angle pin connector 2 pin straight pin connector 6 32 x 3 8 machine screw 6 32 nuts p c board ...

Page 66: ... CEl nESE I p I no j nXQl OUT 10 07 o 27 2 I C l 9 Rl n5 AnE 3 3K 1 K1 I S A 24 PIN S JUMPEn WInE PAD 11 116 117 A 11 E 1 12 Voo 12 v Vee 5 v 4 J 1 J 2 AND J 3 A 11 E 2 6 PiN S CONNECTOnS 5 J P J U M P E 11 WI n E 6 5 A 4 S W T C H E 5 DIP SWITCH 7 ALL n E SiS TOR SAn E i NOH MS 6 ALL CAP A CIT 0 n S A 11 E I N f 1 nN2 3 31 AND nN3 1 K AnE P U L L U P n E 5 i 5 T 0 11 5 T 0 V cc nN1 3 31 1 15 PULL...

Page 67: ... OF U24 OPI TO PIN 12 OF U25 Igl 8 lU25 9 PARALLEL IN OP6 TO PIN 9 Or J rlN4 15 11 12 17 16 lQl 18 e 9 2gl 19 7 JS 11 5 6 23 22 2 2 3 26 25 1 PULL UP RESISTORS 19l1 OHMS EACH 2 J 5 A 2 6 PIN S CONNEC TOR 3 0 P CON NEe TIN G POINTS TO THE MAIN I OCIRCUIT FIGURE 7 INPUT OUTPUT BOARD OPTIONAL CIRCUIT 1 ...

Page 68: ... P CON NEe TIN GPO I N T 5 T 0 T Ii E MA I N I 0 C IRe U IT 3 T Ii E C n Y5 TAL X TAL HAS A F R EQ U ENe Y 0 F 2 45 toiH z AND ICOM CORPORATIO TITLE AIOll4 4 INP T OUTPLl BOARD OPT I NAL C JRCU IT 2 DR WIN NO Ace 15 2 DR WN Y K T J M CI I CKr RY W lJ UNr JULY 1981 FIGURE 8 INPUT OUTPUT BOARD OPTIONAL CIRCUIT 2 ...

Page 69: ... v 1 U3 G 2 78 P5 3 lC9 VCCI5v 1 U3 7 2 78 P5 3 1 ALL CAPACITO I1S AI1E 1 1Jt 2 0S 1 au s ANOICOM COI POI ATION IITLI AI011 1 1 I NPU I IOUI PUI BOAI O POWE I SUPPLIES OI1AWING N ACO 15 3 OI1AWN BY 1 I AM CHECI EO BY W LEUNG JULY 1981 FIGURE 9 INPUT OUTPUT BOARD POWER SUPPLY ...

Page 70: ...l U23 1 l7CJ II LSI 39 U24 L511l1 o C2 1 EJ U21 L532 D U7 L5244 5 __ U21l1 8253 nrun I lWlL513G 3 31 UI8 8253 1 l2 1 l4 J 4X3 3K OOOO Kl 1 l3 1 l5 DelIII I I Jl I IJP8JP4 1 1 J2 lP5 PI r I I JP7n I U4 c usl L 1489 1 I UJP3 1488 D I l N I D U3 3 3K UG 8251 8251A CGD U36 If e 7 5 U37 D 78 illS c7D D C8 DC9 llf Ill 1 U35 C5 7912 to It I ll 3 31 O CIQ 1 U34 7812 NOTE ALL I lESI5TOl l VALUES AI lE IN O...

Page 71: ... microprocessors such as the 8085 The 8251A is used as a peripheral device and is programmed by the CPU to operate using virtually any serial data transmission technique presently in USB including IBM bi sync The USART accepts data characters from the CPU in parallel format and then converts them into a continuous serial data stream for transmission Simultaneously it can receive serial data stream...

Page 72: ... conclusion of a transmission TxD line will always return to the marking state uhless SBR K is programmed 44 Tx Enable logic enhancement prevents a Tx Disable command from halting trans mission until all data previously written has been transmitted The logic also prevents the transmitter from turning off in the middle of a word When External Sync Detect is programmed Internal Sync Detect is disabl...

Page 73: ...peration It contains the Control Word Register and Com mand Word Register that store the various control formats for the device functional definition RESET Reaet A high on this input forces the 8251A into an Idle mode The device will remain at Idle until a new set of control words is written into the 8251A to program its functional definition Minimum RESET pulse width is 6 tev clock must be runnin...

Page 74: ...olled operation the CPU can check TxRDY using a Status Read oDeration TxRDY is auto matically reset by the leading edge of WR when a data character is loaded from the CPU Note that when using the Polled operation the TxRDY status bit is not masked by Tx Enabled but will only indicate the Empty Full Status of the Tx Data Input Register Trenlmltter Buffer The Transmitter Buffer accepts parallel data...

Page 75: ...t be detected after a chip master Reset Once this has been determined a search for a valid low Start bitl is en abled This feature is only active in the asynchronous mode and is only done once for each master Reset The False Start bit detection circuit prevents false starts due to a transient noise spike by first detecting the fail ing edge and then strobing the lominal center of the Start bit RxD...

Page 76: ...ode and Command Instructions must conform to a specified sequence for proper device operation The Mode Instruction must be inserted immediately following a Reset operation prior to using the 8251A for data com munication All control words written into the 8251A after the Mode In struction will load the Command Instruction Command Instructions can be written into the 8251A at any time in the data b...

Page 77: ...When no data characters have been loaded into the 8251A the TxD output remains high marking unless a Break continuously low has been programmed ONLY EFFECTS T R NEVEA REQUIRES MORE THAN ONE STDPBITJ Figure 8 Mode Inatructlon Formet A ynchronou Mode GENERATED DO D1 D BY 12 1A l t ern L DOES NOT APPEAR RECEIVER INPUT ooDl D 00 THE DATA BUS D START BITSt PA ITY ST BIT IlI Ts L A ynchronou Mode Receiv...

Page 78: ...nchronization is achieved by applying a high level on the SYNOET pin thus forcing the 8251A out of the HUNT mode The high level can be removed after one RxC cycle An ENTE R HUNT command has no effect in the asynchronous mode of operation Parity error and overrun error are both checked in the same way as in the Asynchronous Rx mode Parity is checked when not in Hunt regardless of whether the Receiv...

Page 79: ...ns that require the processor s attention The 8251A has facilities that allow the programmer to read the status of the device at any time during the functional operation The status update is inhibited during status read A normal read command is issued by the CPU with C O 1 to accomplish this function Some of the bits in the Status Read Furmat have identical meanings to external output pins so that...

Page 80: ...LICATIONS OF THE 8251A Figure 14 Aaynchronoue Serlel Intertece to CRT Termlnel DC 9600 Beud Figure 18 Alynchronoul Intertece 10 Telephone L1nee ADDRESS BUS I I I CONTROL BUS I DATA BUS 19 0 0 SYNCHRONOUS TERMINAL 8251 OR PERIPHERAL DEVICE SYNDET ADDFIl SS BUS I CONTROL BUS I I DATA BUS 1 7 0 I 8251 hO f 1 PHONE UNE TiC INTER fACE SYNQET SYNC f MODEM C fi m e 1 TELEPHONE UNE Figure 15 Synchronoul I...

Page 81: ...P rameter Min Max Un Tea Condition V L Input Low Voltage 0 5 0 8 V V H Input High Voltage 2 2 Vee V VOL Output Low Voltage 0 45 V tOL 2 2 rnA Vo Output High Voltage 2 4 V IOH 400 p A IOFL Output Float Leakage 10 A VOUT Vee TO 0 45V I L Input Leakage 10 A V N Vee TO O 45V Icc Power Supply Current 100 rnA All Outputs High CAPACITANCE TA 25 C Vee GND OVI Symbol Parameter Min Max Unit Test Conditions ...

Page 82: ...d 64x Baud Rate 1 lev tTPO Transmitter Input Clock Pulse Delay 1x Baud Rate 15 lev 16x and 64x Baud Rate 3 lev fAx Receiver Input Clock Frequency 1x Baud Rate DC 64 kHz l6x Baud Rate DC 3 0 kHz 64x Baud Rate DC 6 5 kHz APW Receiver Input Clock Pulse Width 1x Baud Rate 2 ev l6x and 64x Baud Rate 1 ev tAPD Receiver Input Clock Pulse Delay lx Baud Rate 15 tev 16x and 64x Baud Rate 3 ev tTxADY TxRDY P...

Page 83: ... following limitations with respect to eLK For Ix Baud Rate tTII orfRx 1 30 tCY For 16x and 64 Baud Rate Tx or fRx 1 4 5 ICY 6 Reset Pulse Width 6 Icv minimum System Clock must be running during Reset 7 Status update can have a maximum delay of 28 clock periods from the event affecting the status TYPICAL OUTPUT DELAY VS CAPACITANCE pF 20 T I t l I t I I I CAPAcnANeE IpF I A C TESTING INPUT OUTPUT ...

Page 84: ... UO COUNTER TARTS MERE I ST AT liT DATA liT OAT IT 1 0 lI i_ ___ J RiC t h MODEl 1 A c 11 MODEl UrtTlAMPLlNO WRITE DATA CYCLE CPU USART TdllOY 1 I hRDY CLEAR I 1 j O DON T CARE DON T CARE DATA INiD I OATASTAlLE Ii W j READ DATA CYCLE CPU USART hRDY J lf c r I hIllOY CU lI iJrr 1 j r DATA OUT 10 O C J JU ___j 20 v 0A U t l i i Lv _ t JIAII J 8 56 FN 1573B ...

Page 85: ...A OUT r pr 10 81 I AR I IRA r CID It I 1 I I 1 _ y I IIIOTE Twc INCLUDES THE RESI ONSE TIMING OF A CONTROL eYTE NOTE 2 TCA INCLUDES THE EFFECT Of CTS ON THE TxEIIIBL ClRCUITRY TRANSMITTER CONTROL AND FLAG TIMING ASYNC MODE hEMPT EXAMPLE FORMAT 1 BIT CHARACTER WITH PARITY 2 STOP BITS w _ j OAlACHA ll DATA CHAR 2 OATACHAR O I TACHAA4 fA EMPTY hlUAOV pINI c o Jr te l i l J l i L j J l r W S8RK T Re l...

Page 86: ...ND FLAG TIMING SYNC MODE Y l l J i c OT 5 _ _ H Ofl U f 11L r 1L 1 I f 5 1 r r S D U IV i D 1 DO C CHO e no l I k o r l f T J ob p itd i1 llir1tt llJ I C f tt t 1 t H _ dO 11 0000 1h h U j l x 9 f X x g x a E 3 Xun 0 _ I I I 1 H ASSvef OIS I I j JU ru 1m L OI ID UlTH flIO I 511 T on RTS OIT ISTAWS 1Tl lYfIOlT r UI 000 1 l Ne c n _ rs 1T TY us s u TY 8 58 AFN 015738 ...

Page 87: ...pheral It uses nMOS technology with a single 5V supply and is packaged in a 24 pln plastic DIP It is organized as 3 independent l6 blt counters each with a count rate of up to 2 MHz All modes of operation are 80ft wafe programmable il CLKO DATA COUNTER Q 0 v GATE 0 BUFFER I aUTO 0 elK 1 w _ V READ COUNTER WRIH GATE 1 Ao LOGIC _OUTl A1 A _ _ J eLK 2 OUT 2 elK 2 GATE 2 CONTROL COUNTER eLK 1 WOAD GAT...

Page 88: ...p timing loops in systems software the programmer configures the 8253 to match his requirements initializes one of the counters of the 8253 with the desired quantity then upon command the 8253 will count out the delay and interrupt the CPU when it has completed its tasks It is easy to see that the software overhead is minimal and that multiple delays can easily be maintained by assignment of prior...

Page 89: ...e configured by the selection of MODES stored in the Control Word Register The counters are fully independent and each can have separate Mode configuration and counting operation binary or BCD Also there are special features in the control word that handle the loading of the count value so that software overhead can be minimized for these functions The reading of the contents of each counter is av...

Page 90: ... one or two bytes depending on the mode selected by the RL bits followed by a rising edge and a failing edge of the cloCk Any read of the counter prior to that falling clock edge may yield invalid data MODE Dallnltlon MODE 0 Interrupt on Terminal Count The output will be initially low after the mode set operation After the count Is loaded into the selected count register the out put will remain lo...

Page 91: ...meout the output goes low and the full count is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decrement the count by 2 until timeout Then the whole process is repeated In this way if the count is odd the output will be high for N 1 2 counts and low for N 1 2 counts MODE 4 Soltwere Triggered Strobe After the mode is set the output will be hi...

Page 92: ...m MODE 1 Progrommoblo Ono Shot MODE 4 Soflworo Trlggorod Slrobe CLOCK CLOCK LOADn r WIl TRIGGER OUTPut OUTPUT _ Lr TRIGOER t Jr OUTPUT GATE OUTPUT L J ____ _ _ D U MODE 2 Roto aonorolor MODE 5 Hordworo Trlggorod Slrobe CLOCI JUU ln Jn n n CLOCK GATE Jr 3 2 W r OUTPUT In 4 3210 J12 013 OUTPUT n 31 r t 2J l 2 1 0141 3 2 1 Olll 2 1 0 OUTPUT RESET t S G A T E 4 3 3 2 1 0 r _ DUTI UTln l U Figure 7 825...

Page 93: ...ng the MODE control word loading as long as the correct number of bytes is loaded in order All counters are down counters Thus the value loaded into the count register will actually be decremented Loading all zeroes into a count register wiH result in the maximum count 216 for Binary or 10 10r BCD In MODE 0 the new count will not restart until the load has been completed It will accept one of two ...

Page 94: ...eading procedure If two bytes are programmed 10 be read then two bytes must be read before any loading WR command can be sent to the same counler Read Operation Chert Al AO RO 0 0 0 Read Counter No 0 0 1 0 Read Counter No 1 1 0 0 Read Counter No 2 1 1 0 Illegal R adlng While Counting In order for the programmer to read the contents of any counter without effecting or disturbing the counting operat...

Page 95: ...Teat Condition V L Input Low Voltage 0 5 0 8 V V H Input High Voltage 2 2 Vcc 5V V __ VOL Output Low Voltage 0 45 V Note 1 VOH Output High Voltage 2 4 V Note 2 IlL Input Load Current 1Q A VIN Vee to OV IOFl Output Float Leakage 10 A VOUT Vee to OV ec Vee Supply Current 140 rnA CAPACITANCE TA 25 C Vee GND OV Symbol Parameter Min Typ Max Unit Test Conditions C N Input Capacitance 10 pF fc 1 MHz ClIO...

Page 96: ...Clock Period 380 dc 380 dc ns tPWH High PuIse Width 230 230 ns tpwL Low Pulse Width 150 150 ns taw Gate Width High 150 150 ns tGL Gate Width Low 100 100 ns tos Gate Set Up Time to CLKt 100 100 ns tGH Gate Hold Time After CLKt 50 50 ns too Output Delay From CLKH4J 400 400 ns DOG Output Delay From Gate 4 300 300 ns NOTES 1 IOL 2 2 rnA 2 OH 4 I A 3 AC timings measured at VOH 2 2 VOL 0 8 4 C l5OpF A C...

Page 97: ...825318253 5 WAVEFORMS WRITE TIMING READ TIMING ctI J 1 1 lw DATA8US _ t ww ctI t I I DATA BUSY HIGH IMPeOA CE CLOCK AND GATE TIMING f n I 1 CLK GAT G OUTPUT 0 f I1 I1 1 100G 8 69 AFN 00745S ...

Page 98: ...assigned the highest interrupt priority It accommodates both single density IBM 3740 and double density IBM System 34 formats with soft sector compatibility Recording can be done on both sides of a diskette thus allowing up to 1 Megabyte of formatted data to be stored on a 2 sided double density diskette Western Digital s FD1793 along with two other supporting chips form the heart of the AFC llOO ...

Page 99: ...As well any speed variations or track to track variations can also be handled better with a PLL Another supporting chip is the write precompensation circuit which contains the remaining part of U5 and a WD2143 U6 The precompensation applies only when the current track number on a double density diskette is greater than 43 Detailed information regarding the uses of the FD1793 WD1691 and WD2143 can ...

Page 100: ...ingle density selected D7 2 SIDED Single sided diskette in drive DO DRSELI Selects drive 0 A Dl DRSEL2 Selects drive 1 B Drive D2 DRSEL3 Selects drive 2 C Command D3 DRSEL4 Selects drive 3 D D4 SIDE 1 Selects side 1 of drive D5 Selects 5 25 drive D6 DDEN Selects single density D7 Enables wait states Jumper Connections The interrupt vector jumper area is located in the upper right hand corner of th...

Page 101: ...ould any adjustments be required they should be performed by qua11fied service personnel connection Qf ni2k Driyes The 50 pin header strip J2 connects all large S drives to the board and the 34 pin header strip Jl if it exists connects all mini 5 25 drives to the board Only the even numbered pins bottom row are used for connection to the drives while the odd numbered pins top row are grounded The ...

Page 102: ...Western Digital Four phase clock generator Western Digital Dual voltage controlled oscillator Dual 4 input NAND Hex inverter Floppy disk controller chip Western Digital Quadruple 2 line to l line multi plexer Octal buffer line driver with 3 state outputs 3 to 8 line decoder demultiplexer Octal D type flip flop Quadruple 2 input NOR Quadruple 2 input NAND Hex inverter Dual D type positive edge trig...

Page 103: ... 47 k ll 10k i 1 6 2 k o 4 7 k f 1 k 1 10 k S 100 k 11 50 k J 1 k n pescription 14 pin IC socket 16 pin IC socket 18 pin IC socket 20 pin IC socket 40 pin IC socket 50 pin right angle pin connector 2 pin right angle pin connector TQ 220 heat sink 6 32 x 3 8 machine screw 6 32 nuts p c board ...

Page 104: ...R 4 I 2 6 I U I R3 L If 11 0 2 iN r5EX 2 0L 8 i IS R2 I i i L5 367 WPR T L L L 8 f11_ 46 j3 I j 1 I I ____ S _ _ 3 6 2 ali J 3 34 181 I_ 18 i 4 2411 WRTDATAb 22 I JR5_RE A jY22 J III vee t ER 5lJ PL Y _ I c k__ lr I r II 1 L D _r I II Voo t _ 1 _ J U 2 2 l I I I 7 I C6 1 7 _ S 10 8 EACH Ie S SU L y CONNECTIONS AnE NOT SHOWN 9 TP TEST POiNT 1 J P JUMPER WI RE 11 RR3 AND Cl1 ARE OPT IONAL _ 1 2 R19 ...

Page 105: ...6Cl15 G8Pf O O 5 1K LSI13 R 7 111 Cln I UI c30L 1 1 78 5 1 L _ _ RRll K 01 0 UG B 0 1 1143 33 1 C5q3 6KTPl Cl R11 0C1Ql L5157 OC4 1 0 471 110CI1 0 Cl T 2 47KCl 0 Cl1 Rl RRl 5 KD U14l g 00 O 8 OC14 4 LSIQl 1 RR4 5 1 Ul 7812 I 5 1 Ql 8U5 I NOTE R9 Dl AND 02 ARE LOCATED ON THE REVERSE SIDE OF THE BOARD ALL RESISTOR VALUES ARE IN OHMS ALL CAPACITOR VALUES ARE IN MICROFARADS UNLESS SPEC IFIED 01 02 ARE...

Page 106: ...nd 1797 are identical to the 1791 and 1793 except a side select output has been added that is controlled through thecommand Register a w ID SYSTEM DESIGN The first consideration in Floppy Disk Design is to de termine which type of drive to use The choice ranges from single density single sided mini floppy to the 8 double density double sided drive Figure 2 illustrates the various drive and data ca...

Page 107: ...e user has the option of checking the busy bit or use the INTRa Line to denote command comple tion The Busy bit will be reset whenever the 179X is idle and awaiting a new command The INTRa Line once set can only be reset by a READ of the status register or issuing a new command The MR Master Reset Line does not affect INTRa 2 The Ao A Lines used lor register selections can be configured at the CPU...

Page 108: ...ion is a function of the drive Some manufacturers recommend Precompensating the 5V4 drive while others do not With the 8 drive Precompensation may be specified from TRACK 43 on or in most cases all TRACKS If the recommended Precompensation is not specified 3 check with the manufacturer for the proper configura tion required The amount of Precompensation time also vanes A typical value will usually...

Page 109: ...while the RClK input provides a window or strobe signal to clock each RAW READ pulse into the device An ideal Data Separator would have the leading edge of the RAW READ pulse occur in the exact center of the RClK strobe Motor Speed Variation Bit shifts and read amplifier recovery circuits all cause the RAW READ pulses to drift away from their nominal positions As this occurs the RAW READ pulses wi...

Page 110: ...used to terminate a multiplp sector command or to Insure Type I status In the status register The lower four bits of the oommand determine the conditional interrupt as follows 10 NOT READY TO READY TRANSITION 1 READY TO NOT READY TRANSITION 1 EVERY INDEX PULSE 1 IMMEDIATE INTERRUPT Regardless of the conditional interrupt set any com mand that is currently being executed when the Forced Interrupt c...

Page 111: ...K TIME PER TRACK PER DISK 5V4 SINGLE 1 3125 109 375 64 Ls 2304 80 640 5114 DOUBLE 1 6250 218 750 32 Ls 4608 161 280 5114 SINGLE 2 3125 218 750 64 Ls 2304 161 280 5114 DOUBLE 2 6250 437 500 32 Ls 4608 322 560 8 SINGLE 1 5208 401 016 32 Ls 3328 256 256 8 DOUBLE 1 10 416 802 032 16 Ls 6656 512 512 8 SINGLE 2 5208 802 032 32 Ls 3328 512 512 8 DOUBLE 2 10 416 1 604 064 16 Ls 6656 1 025 024 Based on 35 ...

Page 112: ...IGURE 4A FM RECORDING HEX 02 BIT 0 BIT 1 BIT 2 o BIT 3 BIT 4 o BIT 5 o BIT6 BIT 7 o RULE 1 WRITE DATA BITS AT CENTER OF BIT CELL IF A 1 2 WRITe CLOCK BITS AT LEADING EDGE OF THE BIT CELL FIGURE 48 MFM RECORDING BIT 0 BIT 1 8112 o 8113 8114 o BIT 5 o 81T6 BIT 7 o HEX D2 RULE 1 WRITe DATA BITS AT CENTER OF BIT CELL IF A 1 2 WRITe ClOCK BITS AT LEADING EDGE OF BIT CELL IF A NO DATA BIT HAS BEEN WRITT...

Page 113: ...NLV ptN 33 USED AS VFOE AND WF SIGNAlS 10K 741S01 33 WF FROM DRIVE 179X 30 WG TO DRIVE PIN 33 USED AS A WF SIGNAl ONLY 10K 7438 J 741S175 12 e _EAR __ LY t WO tc U 3io1DI 2 I J fP lQ r 2Q 1 t4AL rr lo 1 4Q EARLY I 1 1 19 0 40 LR LATE f _L 74LS02 FD179X WD2143 WOTO DRIVE 11 2 n PRECOMP ADJUST 8 IN 81 Af2 8 1 _ 17 J PW FIGURE 6 179X WRITE PRE COMP 8 ...

Page 114: ...ION OF WD PULSE VALID BEFORE LEADING EDGE OF WD WRITE PRE COMP TIMING FOR MFM WRITE PRE COMP TIMING FOR FM FIGURE 7 WRITE PRE COMP TIMING BIT CELL 0 I BIT CELL 1 I BITCELL2 IBITCELL3 BIT CEll 4 BIT CELL 5 IBIT tELL 6 IBITIELL 7 I BIT CELL 8 I BIT CELL 9 II II 1 J I 200NS 5lJl Id Q IJ kI Icl kI W Z C m EARLY n n n LATE n n C EARLY n I I n C l ATE n n C NOM1NAL ii I 53 II WD r 1J FIGURE 8 PRECOMP TI...

Page 115: ... 500n 100ns 2SOn l _ I I I _1 fI eLK 2_ we OOEN 0 o 5On8 3On FIGURE 9 WD CLK RELATIONSHIP FOR WRITE PRECOMP USE I _ ITO 11511 om WRITE tTO DRIVE FIGURE 10 DIGITAL WRITE PRECOMP CIRCUIT IAAOVIDED COURTESY OF MPI OKLAHOMA CIlY Ol 73112 10 ...

Page 116: ... I RAW READ P J 27 RAW READ FROM DRIVE 179111793 11 CJ 26 f RCLK LO T T 15 A 5 f1i B 7 3 C Q CO NU AG 10 C r 0 74L 74 DDEN CU 5 CO C 74lS193 CRYCLK TYPE DDEN CRYClK FM 1 8MHz 5 MFM 0 8 MHz 5 FM 1 4 MHz FIGURE 11 COUNTER SEPARATOR 11 ...

Page 117: ..._ 5 I 4 K o 0 74lS 4 READ DATA FROM DRIVE FREE RUN ACTION TAKEN NONE RETARD BY 1 COUNT ADVANCE BY 2 COUNTS RETARD BY 2 COUNTS ADVANCE BY 1 COUNT ADDRESS DATA 00 01 0 0 0 02 03 03 04 03 OS 04 06 OS 07 0 06 DB 09 00 OA DC OB OE OC OF 00 OF ot 00 OF 01 10 01 11 02 12 03 04 14 OS 15 06 07 06 09 L OA A OB B OC C 00 10 OE E OF 1F 00 FIGURE 12 179X DATA SEPARATOR PROVIDED COURTESY OF ANDROMEDA SYSTEMS PA...

Page 118: ...VFQ CLK 2 OR 4 R W 27011 1 2 W C71 C73 C74 R21 47 F 047uF 1300j lF 10KO 2 0 1 0 R12 I t 806H I 9 1 0 R11 U2 14011 0 2N2907A R14 20K L R13 l ll R oTP1 R19 3A8KO 4 2 2KII 100 3 5 74S112I _f I_ _W _i I J VFO CLK 6 CLK STEERING 1 2 K 15 R R15 5 1Kll 2 R30 5 lKll 0 S 11 J jJ j 3 CLK 12 K I R29 26502 1KO 19150NSEC1 1 ClR Q II TP2 I Ul l 14 15 C89 82 lF C70 1 READ DATA 150j lF 4 I _ 3 26502 ClR I Ul I l ...

Page 119: ... I _I WD iOK 3 47K 100K EAALY 17 EARLY _ 1ANG BIAS VOLTAGE 13 PU 18 ADJ LATE I _I LATE E I 14 PO TG43 9 TG43 a r6 9 5 8 I 33 F L STB VFOE f o If H vFaE WF _ r 47K Vss m NOTE 3 33n 19 312141 TO J WPRTf 36 _11 3 5 171 DAIVE P 35 I 11 xl 04 03 02 01 vcc 5 1 1 _ WD2143 01 12 17 l1pw Vss 9 16 DIRC TAQO 34 t KV PRECOMP ADJ 10K _ 15 32 v w 1 5 l STEP READY r O J iE 20 c J y 25j Lsec 5 1 All 2 SPE CAPTI L...

Page 120: ... Flag Bit 3 h 1 Load head at beginning h 0 Unload head at beginning V Verify flag Bit 2 V 1 Verify on destination track V 0 No verify r r0 Stepping motor rate Bits 1 0 Refer to Table 1 for rate summary u Update flag Bit 4 u 1 Update Track register u 0 No update FLAG SUMMARY TYPE II III COMMANDS m MUltiple Record flag Bit 4 m 0 Single Record m 1 MUltiple Records a Data Address Mark Bit 0 ao 0 FB Da...

Page 121: ...onsibility is assumed by Western Digital Corporation lor its use nor any infringements of patents or other rights of third parties which may resul1 from its use No license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation Western Digital Corpora tion reserves the fight 10 change said circuitry at any time without notice 3128 REDHILL AVENUE BOX ...

Page 122: ...NCORPORATES ENCODING DECODING AND ADDRESS MARK CIRCUITRY FD179214 IS SINGLE DENSITY ONLY FD1795 7 HAS A SIDE SELECT OUTPUT 179X 02 FAMILY CHARACTERISTICS FEATURES 1791 1793 1795 1797 Single Density FM X X X X Double Densitv MFMl X X X X True Data Bus X X Inverted Data Bus X X Write Precomp X X X X Side Selection Output X X APPLICATIONS FLOPPY DISK DRIVE INTERFACE SINGLE OR MULTIPLE DRIVE CONTROLLE...

Page 123: ...ing dou ble sided drives and the 1792 and 1794 are Single Density Only versions of the 1791 and 1793 On these devices DDEN must be left open PIN NUMBER PIN NAME SYMBOL FUNCTION 20 POWER SUPPLIES Vss 21 Vee 40 Von COMPUTER INTERFACE 2 WRITE ENABLE WE 3 CHIP SELECT CS 4 READ ENABLE RE 19 MASTER RESET 1 NO CONNECTION 5 6 7 14 24 REGISTER SELECT LINES DATA ACCESS LINES CLOCK NC MR AO A1 DALO DAL7 ClK ...

Page 124: ...otors 23 HEAD LOAD TIMING HLT When a logic high is found on the HLT input the head is assumed to be engaged 25 READ GATE 1791 3 RG A high level on this output indicates to the data separator circuitry that a field of zeros or ones has been encountered and is used for synchroni zation 25 SIDE SELECT OUTPUT SSO The logic level of the Side Select Output is directly 1795 1797 controlled by the S flag ...

Page 125: ...ver a Write Command is received A logic low terminates the command and sets the Write Protect Status bit 37 DOUBLE DENSITY DDEN This pin selects either single or double density op eration When DDEN 0 double density is selected When DDEN 1 single density is selected This line must be left open on the 1792 4 ORGANIZATION The Floppy Disk Formatter block diagram is illus trated on page 5 The primary s...

Page 126: ...tus bits is a function of the type of command previously executed This register can be read onto the DAL but not loaded from the DAL CRC Logic This logic is used to check or to gener ate the 16 bit Cyclic Redundancy Check CRC The polynomial is G x x16 x12 x 1 The CRC includes all information starting with the address mark and up to the CRC characters The CRC register is preset to ones prior to dat...

Page 127: ...facing with the mini floppy the ClK input is set at 1 MHz for both single density and double density When the clock is at 2 MHz the stepping rates of 3 6 10 and 15 ms are obtainable When ClK equals 1 MHz these times are doubled 6 HEAD POSITIONING Five commands cause positioning of the Read Write head see Command Section The period of each positioning step is specified by the r field in bits 1 and ...

Page 128: ... be used to inform phase lock loops when to acquire syn chronization When reading from the media in FM RG is made true when 2 bytes of zeroes are detected The FD179X must find an address mark within the next 10 bytes otherwise RG is reset and the search for 2 byte of zeroes begins allover again If an ad dress mark is found within 10 bytes RG remains true as long as the FD179X is deriving any usefu...

Page 129: ...is set When a command is completed an interrupt is generated and the Busy status bit is re set The Status Register indicates whether the com pleted command encountered an error or was fault free For ease of discussion commands are divided into four types Commands and types are sum marized in Table 2 BITS TYPE COMMAND 7 6 5 4 3 2 1 0 I Restore 0 0 o 0 h V r I r I Seek 0 0 0 1 h V rI fl I Step 0 0 1...

Page 130: ... to the Track Register if there is a match and a valid ID CRC the verification is complete an interrupt is generated and the Busy status bit is reset If there is not a match but there is valid ID CRC an interrupt is generated and Seek Error Status bit Status bit 4 is set and the Busy status bit is reset If there is a match but not a valid CRC the CRC error status bit is set Status bit 3 and the ne...

Page 131: ...stepping pulse to the disk drive The stepping motor direction is the same as in the previous step command After a delay determined by ther ro field a verification takes place if the V flag is on If the u flag is on the Track Register is updated The h bit allows the head to be loaded at the start of the command An interrupt is generated at the completion of the command STEP IN Upon receipt of this ...

Page 132: ... Table Sector Length Number of Bytes Field hex in Sector decimal 00 128 01 256 02 512 03 1024 Each of the Type II Commands contains an m flag which determines if multiple records sectors are to be read or written depending upon the command If m 0 a single sector is read Or written and an inter rupt is generated at the completion of the command If m 1 multiple records are read or written with the s...

Page 133: ...g of the command dependent upon the value of this flag READ SECTOR Upon receipt of the Read Sector command the head is loaded the Busy status bit set and when an 10 field is encountered that has the correct track number correct sector number correct side number and correct CRC the data field is presented to the computer The Oata Address Mark of the data field must be found within 30 bytes in singl...

Page 134: ... Status Bit is set and a byte of zeros is written on the disk The command is not terminated After the last data byte has been written on the disk the two byte CRC is computed internally and written on the disk followed by one byte of logic ones in FM or in MFM The WG output is then deactivated TYPE III COMMANDS READ ADDRESS Upon receipt of the Read Address command the head is loaded and the Busy S...

Page 135: ...M OOEN 1 IN MFM OOEN Ol 00 thrll F4 Write 00 thrll F4 with GlK FF Write 00 thru F4 in MFM F5 Not Allowed Writp 11 1 in MFM Pmsp t CRC F6 Not Allowed Write C2 in MFM F7 Generate 2 CRG bytes Generate 2 CRG bytes F8 thrll FB Write F8 thrll FB Glk G7 Presp t GRG Writp F8 thru FB in MFM FG Write FG with Clk 07 Writp Fe in FM FD WritP FD with Glk FF Writp FO In FM FE Write FE GIl G7 Preset GRG Wr tp FE ...

Page 136: ...ELAY ISMS HLT _1 YES TG43 UPDATE READ TRACK NO NO NO INTRQ RESET BUSy NO READ ADDRESS YES SHIFT ONE BIT INTO DSR HAVE 6 BITS BEEN ASSEMBLED YES IS DR EMPTY YES TRANSFER DSR TO DR SET ORQ YES NO SET INTRQ RESET BUSY SET LOST DATA BIT If TEST NO DELAY If TEST 1 and CLK 1 MHZ 30 MS DELAY TYPE III COMMAND Read Track Address 15 ...

Page 137: ...nterrupt to clear on a subse quent Load Command Register or Read Status Register STATUS DESCRIPTION Upon receipt of any command except the Force In terrupt command the Busy Status bit is set and the rest of the status bits are updated or cleared for the new command If the Force Interrupt Command is received when there is a current command under execution the Busy status bit IS reset and the rest o...

Page 138: ... continues from one index mark to the next index mark Normally whatever data pattern appears in the data register is written on the disk with a nor mal clock pattern However if the FD179X detects a data pattern of F5 thru FE in the data register this is interpreted as data address marks with missing clocks or CRC generation For instance in FM an FE pattern will be interpreted as an ID address mark...

Page 139: ...1 1 F7 2 CRCs written 22 4E I 12 00 F5 1 FB Data Address Mark 25 DATA _ 5 2 CRCs written I Wnte bracketed field 26 times Continue writing until FD179X interrupts out I Approx 598 bytes FM MFM Gap I 16 bytes FF 32 bytes 4E Gap II 11 bytes FF 22 bytes 4E 6 bytes 00 12 bytes 00 3 bytes A1 Gap III 10 bytes FF 24 bytes 4E 3 bytes Ai 4 bytes 00 8 bytes 00 Gap IV 16 bytes FF 16 bytes 4E Byte counts must ...

Page 140: ... RE Pulse Width 400 nsec CL 50 pf TDRR DRa Reset from RE 400 500 nsec TIRR INTRa Reset from RE 500 3000 nsec See Note 5 TDACC Data Access from RE 350 nsec CL 50pf TDOH Data Hold From RE 50 150 nsec CL 50pf lfi OR n uS _ I TORR INTAQ 1 __ f SERVIC o 0 CS t tJo J IDAU V LID bO NOTE cs v BE PEA NENTlV TIED LOW If DESIIlED T ME DOUBLES _EN CLOCK 1 SERVICE WORST CASE HI 27 5 uS MfM 135 uS READ ENABLE T...

Page 141: ...s 70 C Tx RCLK hold to Raw Read 40 nsec See Note 1 TX2 Raw Read hold to RCLK 40 nsec INPUT DATA TIMING f 1 I i RAW E D U U 1 I RCl I I I 1 j I j NOMINAL DISKETTE MODE DDEN elK T T T S MFM 0 2 MHz 1 1 2 S FM 1 2 MHz 2 2 4 5 MFM 0 1 MHz 2 2 4 5 FM 1 1 MHz 4 4 S 1 I f I r f 1 NOTE CS MAY BE PER MIENTI Y TIE LOW If DrSIRED 2 WHEN WRITING lATA Nro S CTOR TRACK OR DA fA RE STER USE CANNQT REAfl THIS R G...

Page 142: ...4 IJ sec ClK Error Ts Early late to Write Data 125 nsec MFM Th Early late From 125 nsec MFM Write Data Twf Write Gate off from WD 2 IJ sec FM 1 IJ sec MFM Twdl WD Valid to Clk 100 nsec ClK 1 MHZ 50 nsec ClK 2 MHZ Twd2 WD Valid after ClK 100 nsec ClK 1 MHZ 30 nsec ClK 2 MHZ I elK IMHZI WD elK 2MHZj WD r 500 NS _ _ 1 1 L WX13 Wffij J Twdl 1 1r Twd2 L _ _ r 125 r 125 1 I __ JI I _ __ a_ TWdI I I Twd2...

Page 143: ...idth 10 Lsec MISCELLANEOUS TIMING NOTES 1 Pulse width on RAW READ pIn 27 IS normally 100 300 ns However pulse may be any width if pulse IS entirely wltnln window If pulse occurs In both windows then pulse width must be less than 300 ns for MFM at ClK 2 MHz and 600 ns for FM at 2 MHz Times double for 1 MHz 2 A PPl Data Separator IS recommended for 8 MFM 22 3 tbc should be 2 Ls nominal In MFM and 4 ...

Page 144: ...e This bit is an inverted copy of the IP input SO BUSY When set command is in progress When reset no command is in progress STATUS FOR TYPE II AND III COMMANDS BIT NAME MEANING S7 NOT READY This bit when set indicates the drive is not ready When reset it indicates that the drive is ready This bit is an inverted copy of the Ready input and ored with MR The Type II and III Commands will not execute ...

Page 145: ...Information Iumished by Western Dig al Corporation is believed 10 be accurate and reliable However no responslbil is assumed by Westem DIgital Corporation lor lis use nor any Infringements 01 patents or other rights of third parties which may resun from lis use No lioense is granted by implication or otherwise under any patent or patent rights 01 Westem Digital Corporation Westem Dig al Corporatio...

Page 146: ...179X Family 01 Floppy Disk Controllers to a drive With the use 01 an extemal veo the WD 1691 will generate the RCLK signal lor the WDl79X while providing an adiustmant pulse PUMP to control the VCO lrequency vrn E VW de multiplexing is also accom plished and Write Precompansalion signals have been in cluded to interface directly with the WD2143 Clock Generator The WD1691 is implemented in N MOS si...

Page 147: ...i I 9 I TRACK 43 TG43 Ties directly to the FD179X TG43 P If Write Precompen sation is reqUIred on TRACKS 44 76 I I I 10 V V Ground I Composite clock and data stream input from the dnve 11 READ DATA RDD i 12 READ CLOCK RCLK signal generated by the WD1691 to be tied to the I RCLK i FD179X RCLK pin 13 PUMP UP PU Tn state output that will be forced high when the WD1691 requires an Increase in veo freq...

Page 148: ... high when this occ causing the WD2143 01 to start its pulse gen eration 2 is used as the write data e d se on nominal Early Late is used for early and 4 3 is used for late The leading edge of P4 resets the STB line inDaD Npation of the next write data pulse When TG43 0 or 1 Pre compensation is disabled and any transitions on the WDIN line will appear on the WDout line If write precompensation is ...

Page 149: ...ARAMET _ _ M IN _j T Y P _ M A X r_U N IT t __T_E_S_T_C_O_N_D_IT_IO_N_S __ i I V I Input Low Voltage 0 2 0 8 V i V Input High Voltage I 2 0 V I Voc Output Low Voltage I 0 45 V lac 3 2MA VO Hint Level Output Voltage i 24 V lo 2ool a I Veo i Supply Voltage J j 5 5 0 5 5 V I Icc I Supply Current 40 100 MA All outputs open _ _ _ _ l L _ _ _ AC ELECTRICAL CHARACTERISTCS TA 0 0 to lO C Vee 5V 10 O Vss O...

Page 150: ... WDiN 1l I n n n I I EARLY n LATE n U U C1 i i2 00 G4 STB WDOUT n n n NOM EARLY LATE NOM TG43 1 DDEN 0 TG43 0 DDEN 1 WDIN WDOUT WRITE DATA TIMING MFM _ nL __n _ I I n n 1I II L _Wp_j _ II 11 WRITE DATA TIMING FM 5 ...

Page 151: ...I Adjust the bias voltage poten tiometer for 1 4V on pin 2 of the 74S124 Then adjust the range control to yield 4 0MHZ on pin 7 of the 74S124 RAW DATA c 74LS04 1771 01 l XTDS 1691 11 RDD 74LS08 12 RCLK 27 FDDATA 26 FDCLOCK J 15 DDEN f N C FIG 1 WD1691 to FD1771 01 INTERFACE SUBSTITUTING VCO s There are other VCO circuits available that may be sub stituted for the 74S124 The specifications required...

Page 152: ...LK F2 ROD 7 J I 5 WD1691 WG WG 74LS629 2 1 FC WDIN WD SOK 3 47K lOOK EARLY 17 EARLY RNG BIAS VOLTAGE 13 PU 18 ADJ I LATE LATE E 14 PO 9 8 6 91 TG43 TG43 5 STB 8 C VFOE VF08WF I 47K VSS 10 NOTE 3 33n Q i 53 52 01 MR 191324 TO J 36 n WPRT 1 3 5 7 DRIVE 11 J IP 35 CJ Il xl 04 03 02 01 Vee 5 17 WD2143 01 VSS 16 34 12 flpw DIRC TROO PRECOMPADJ 5K 15 32 n ESISTORS v w 5 STEP READY IFICATIONS URE RANGE 2...

Page 153: ...nllIon Is _ to be _ _ and _ _ no I mod by _lligIIIII euo _ for ill nor OIlY bi or _ or rlghbi 01 _ _ whOlh may horn ill No _ Is granIOd by Ir llI_ or _ _ OIlY __ or __ rlghbi or _ llIgltill CotponllIon _ DigItoI CotponllIon _ _ tho rlghl to cIlongo _ cIn uIlry at Iny timo _ 3128 REDHILL AVENUE BOX 2180 NEWPORT BEACH CA 92663 714 557 3550 TWX 910 595 1139 ...

Page 154: ...widths are Ii controlled by tying an external resistor to the proper w f control inputs All pulse widths may be set to the same width by tying the lPW line through an exter nal resistor Each pulse width can also be individu ally programmed by tying a resistor through the appropriate III1PW 1Il4PW control inputs In addi tion the OSC OUT line provides a TTL square wave output at a divide by four of ...

Page 155: ...can be left open If IWW is used External resistor input to control all phase outputs to the same pulse widths 5V 5 power supply input DEVICE OPERATION Each of the phase outputs can be controlled individually by typing an external resistor from G1 PW G4PW to a 5V supply When it is desired to have G1 through G4 outputs the same width the 01 PW 04PW inputs should be left open and an external resistor...

Page 156: ...143 01 10 NC XTAL1 TTL SQUARE WAVE OPERATION 5 13 2 1 1 14 4 2 2 WD2143 01 15 6 3 3 16 8 4 _ 4 INDIVIDUAL PULSE WIDTH OUTPUTS 10K 3D WD 1Q EARLY ClK 4Q NOMINAL 7438 f EARLY 10 74LS175 7438 LATE LATE 2D 2Q 4D 3Q f 179X 6 5 7438 FD ClR 1 CONTROLLER V CC 02 I 11 XTAL2 0 1 TI E 6 3 XTAL1 2 WD2143 01 n 3 4 1 4 17 0 4 12 GND PRECOMP ADJUST 19 WRITE PRECOMP FOR FLOPPY DISK 3 WD TO DRIVE ...

Page 157: ...NS Absolute Maximum Ratings Operating Temperature Voltage on any pin with respect to Ground Power Dissapation Storage Temperature 00 to 700 C 0 5 to 7V 1 Watt 550 to 1250 C 4 Note Maximum ratings indicate limits beyond which permanent damage may occur Continuous operation at these limits is not intended and should be limited to the DC electrical characteristics specified ...

Page 158: ...urrent 80 ma All outputs open SWITCHING CHARACTERISTICS Vee 5V 5 GND OV TA 0 to 70 C SYMBOL PARAMETER MIN MAX UNITS CONDITIONS Ted XTAL in to OSC out t 100 NS Tpd OSC out to J1 100 NS SYMBOL PARAMETER MIN MAX UNITS CONDITIONS Tpw Pulse Width any output 100 NS CL 30pf JPW 5K Tn Non Overlap Time 20 NS Tpr Rise Time any output 30 NS CL 30pf Tpf Fall Time any output 25 NS CL 30 pi TFR OSC In Frequency...

Page 159: ...0 be accurate and reliable However no responsibility is assumed by Western Digital Corporation for its use nor any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation Western Digital Corpora tlon reserves the right 10 change said circuitry at any ti...

Page 160: ...The Keyboard Terminal Manufactured by Volker Craig Limited ...

Page 161: ... volker craig Iimted 266 MarSland Drive Walerloo Ontario N2J 3Z1 Canada a 519 9300 Telex 069 55327 Toronto ftl 16 456 2070 OPERATOR S MANUAL VIDEO DISPLAY TERMINAL VC404 ...

Page 162: ... Control P X Y Cursor Addressing Escape 2 3 Turn On Procedure 2 4 Modes of Operation Local Half Duplex Remote Full Duplex Remote TransparentiTape 2 5 Communications Interface Recommended EIA Cabling Lengths 2_6 Modems and Acoustical Couplers 3 INSTALLATION 3 1 Initial Inspection 3 2 Claims for Transit Damage 3 3 Installation 4 SALE SERVICE REPORT 4 1 Warranty 4 2 Service Requests APPENDIX A Direct...

Page 163: ... Way cursor flashing or steady block or underline selectable Front panel controls Power OtflOn Local Remote Half Full Duplex Roll Page ASCII APL switches TransparentfTape Mode switch allows display of 95 or 128 characters All control codes displayed when mode is On Bottom line entry in Roll Mode Page overwrite in Page Mode Automatic word wrap around on video display after the 80th character positi...

Page 164: ...ters and control functions For example Control M executes a carriage return Characters repeat automatically if the key held depressed for more than 75 seconds APPENDIX F shows keyboard layouts BREAK The data output lines are put into a space condition for as long as the key is depressed CONTROL CHARACTERS Control characters are transmitted by depressing the CTRL key and the character key simultane...

Page 165: ...uter through the input output connectors on the rear panel LOCAL MODE may be used for testing keyboard functions or working in an off line mode Rev 3 HALF DUPLEX REMOTE In this mode data is simultaneously displayed on the screen and transmitted to the computer each time a key is depressed FULL DUPLEX REMOTE in this mode two way communications exists between terminal and computer When a key is depr...

Page 166: ...el connector marked VIDEO to monitor If remote slave mOnitor is required Impedance 75 ohms 3 One of the foliowing interfaces is required A An RS232C CCITI V 24 25 pin connector and cable from central computer multiplexer or external modem to the rear panel connector marked SERIAL DATA B If a 20 mA current loop interface is required connection is made to the same connector using a special interface...

Page 167: ... offset by 20 Hex X POSITION CHARACTER X POSITION CHARACTER V POSITION CHARACTER 0 Space 41 I 0 Space 1 42 J 1 2 43 K 2 3 44 L 3 4 45 M 4 5 46 N 5 6 47 0 6 7 48 P 7 8 49 Q 8 9 50 R 9 10 51 S 10 11 52 T 11 12 53 U 12 13 54 V 13 14 55 W 14 15 56 X 15 16 0 57 Y 16 0 17 1 58 Z 17 1 18 2 59 I 18 2 19 3 60 19 3 20 4 61 I 20 4 21 5 62 circumflex 21 5 22 6 63 underscore 22 6 23 7 64 grave accent 23 7 24 8...

Page 168: ... extinguish The 25 pin female D connector signal descriptions and assignments follow RS232C CCITT V 24 pin conventions viewed as a modem port The connector is located on the rear panel 4 COLOURED DISPLAY SCREEN OPTION CDS This option allows the selection of a coloured anti glare display screen instead of the sfandard grey white display Specify amber or green 25V S P B B B B B B B a 1 or 2 a r Stop...

Page 169: ...S BACKPLANE BOARD BAC 1 It is possible to operate the terminal on a line voitage of 230VAC or 20V or 115VAC or 10V At either voltage the frequency may be 50 or 60 Hertz The video refresh is not affected and this is separately adjustable At the rear left corner of the main printed circuit board when viewed from the front two pairs of terminal posts can be seen For 230V operation the b ack yellow an...

Page 170: ... LOCAL PF1 PF2 PF3 Pf PF 5 PF6 PF7 PFB PF9 PF 10 PF 11 PF 12 I I 1 e 1 ESC SPACE BREAK 7 8 9 1 2 3 4 5 6 7 8 9 0 TAB I Q Iw I EIAITlyIUIIIOlplll 1 RETURN IRUB 4 5 6 OUT PRINT eA 1 I IOIFIGIHIJIKILI I Il LINE t 1 2 3 ONLY A S FEED HOME OTAl SHIFT I z xlclvIBINIMI I I SHIFT CLEAR g WITH OPTION SPI TYPEWRITER lAYOUT WITH NUMERIC PAD AND FUNCTION KEYS OPTION KB1 Rev 3 ...

Page 171: ... I 6 F V f 1 11 1 I b 11J 1 7 G I d llJ li 0 H I 1 h I_I l 1 1 I g I 1 1 1 I 1 c J 7 J J 1 1 k 1 1 fa L 1 1 J1 t l J m I l f t n I C 0 0 UPPER lOWER CASE ASCII STANDARD 0 p 1 J A Q 0 t B R 3 n r c j 4 l II T 5 E E U 6 u F V J I G J I 8 J H I J I 9 to I Irl I a C J Z I of 0 I L J 1 I t t l T 0 I TYPEWRITER PAIRED APl OPTION APl ...

Page 172: ...5 e U 45 E 35 5 25 5 o o i 14 24 u 1 1 1 t t t l J Nm j 5 iK rt ll r T t j I ENQ E kURSOR U 05 RIGHT 1S o o 6 SYN iACK F CLEAR v 06 rr 9 m l 26 6 36 F 46 v v 76 o 7 ETB BEL G CLEAR W K J 07 gJ 9 Q j m I 27 7 37 G 47 W 57 9 67 w 77 o o o 8 S rCU H CAN r I I 08 mf hr t m 28 8 36 H 46 x 5B h 56 x 78 1 o o o o 9 10 1 o 1 o o 11 12 1 _ E I VT B 3C __ Ie L F I _ DC C 2B 2C 3B 3C K L 4 4C 5 5C k 6 6C j 7...

Page 173: ...r control command _______ __ __ EOl Clear to End of Lin Eq o _ _o Screen _On rece pt __ f2onl __ El _ _ r f l __ _r np r or key _ Front Panel Power Off On Display Brightness Rear Panel Baud Rate Parity Transparent Tape Mode Keyboard local Remote Half Full Duplex Roll Page ASCIlIAPL Power 115 10 VAt 50 60Hz 50VA Normai Operating Power 2ACSA Ap proval maxlmum fnpuf6 u rrent unit and attached periphe...

Page 174: ...The Printer Manufactured by NEe Information Systems Inc ...

Page 175: ...spinwriterTN TERMINALS OPERATOR S GUIDE EC NEe Infotmation Srsfems h DOC NO 10003 01 n ...

Page 176: ...nufacturing reproduction use and sales rights thereto and to any article disclosed therein except to the extent rights are expressly granted to others The foregoing does not apply to vendor proprietary parts Specifications remain subject to introduction of design improvements change to allow the pydght 1979 NEC Informat on Systems Inc 5 Militia Drive Lexington MA 02173 Printpd in U S A ...

Page 177: ... Control Section 2 7 POSITIONING AND PRINTING ADJUSTMENTS 2 8 LOADING INSTRUCTIONS 2 10 Friction Feed Paper Loading 2 12 Pin Feed Paper Loading 2 12 Forms Tractor Paper Loading 2 13 2 5 2 6 2 7 2 8 SPINWRITER PREPARATION TYPICAL OPERATING PROCEDURES SELF TEST MODE TROUBLESHOOTING GUIDE 2 13 2 14 2 14 2 16 CHAPTER 3 MAINTENANCE AND REPLACEMENT PROCEDURES 3 1 3 2 3 3 3 4 MAINTAINING HIGH QUALITY PRI...

Page 178: ...3 5 3 6 3 7 CONTENTS contd FORMS TRACTOR ASSEMBLY REMOVAL PIN FEED PLATEN REMOVAL FRICTION PLATEN REMOVAL Pa9 3 4 3 6 3 7 APPENDIX A APPENDIX B MODELS 5510 20 MODELS 5515 25 A 1 B 1 GLOSSARY Glossary l ...

Page 179: ...l Friction Feed Attachment Removal Right Side Only Forms Tractor Assembly Removal Pin Feed Platen Removal Friction Platen Removal TABLES Title SPINWRITER Terminals Specifications Operator Control Panel Troubleshooting Guide CTRL Control Key Functions ESCAPE Key Funct ions Horizontal Tab Function Absolute Vertical Tab Functions Spacing and Form Advance Control ASCII Coding Charts Diablo Compatible ...

Page 180: ...Model 5510 SPINWRITER Model 5520 SPINWRITER ...

Page 181: ...network the SPINWRITER can communicate in either half duplex or full duplex mode at rates up to 1200 baud The printing element used by the SPINWRITER is a unique reinforced plastic thimble which contains up to 128 fully formed character s of var ious type faces Thimbles that contain up to 125 characters have a cut out so that you can see the last character printed The rib bons used are made of bla...

Page 182: ...0 110 200 300 110 300 600 128 characters maximum 136 columns at 10 characters in 163 columns at 12 characters in 16 in maximum 0 027 in maximum 400 ms maximum 120 positions in 48 positions in 40 ms per 1 6 in plus 53 ms settling 16 ms at 12 characters in Horizontal and vertical in any direction 5 step switching by operator 3 levels by operator Overall Dimensions Width Height Depth 5510 Depth 5520 ...

Page 183: ... 10 000 ft Storage Sea Level to 25 000 ft Acoustic Noise 67 dBA without Covers 60 dBA with Covers INTERFACES Model 5510 20 RS 232 C Current Loop 5515 25 Diablo Compatible Plus Models 1610 1620 RS 232 C Current Loop Xerox Compatible Plus Models 1700 1710 1 3 RELATED DOCUMENTS The following documents relating to the SPINWRITER Terminals are available from NEC Information Systems Inc SPINWRITER Termi...

Page 184: ...l Lever Power Supply Pressure eail Lever Itr j Guide Pulley Pressure Boil Pressure Boit Roller Pressure Roller Cord Holder Carrioge Paper Release Lever PCB S Print Hammer r Print Thimble Acrylic Cover Cover Open Switch Impression Control ii 5S i SWitCh III Ribbon Cartridge Top Cover _ Operator Control pan 1 Middle Cover 2 C Base Cover Keyboard Figure 2 1 SPINWRITER Controls and External Components...

Page 185: ...next form Illuminates if one of following occurs Parity Error Framing Error Cover Open Paper Out Ribbon End Check Condition Buffer Overflow 1 Sounds for about 1 2 second when errors are produced 2 Sounds for about 1 2 second upon receipt of Bell Code 3 For a check condition a repeating audible alarm is produced RESET Spring Loaded Switch Clears ALARM indicator condition is cleared extinguished if ...

Page 186: ...rogram Escape code see 2 2 1 Enables auto line feed when set at ON and when carriage return pressed Selects full or half duplex At full duplex data is trans mitted but no local printing is performed At half duplex data is printed and transmitted Selects odd even mark for mark setting there is no parity check and mark polarity is generated Selects high medium or low communication speed Standard con...

Page 187: ...on Rocker Switch Read only when printer is powered on and SET TOF is pressed 2 When in self test thumbw 1ee switch designation times 10 equals desired column width Applies for settings 03 through 13 Clears SPINWRITER equivalent to power ON OFF clear NOTE The character set is con trolled by an internal program control In REMOTE position SPINWRITER receives and transmits data In LOCAL position the S...

Page 188: ...c Section Most of the keys in the alphanumeric section function like those on a typewr iter For example when you press the SHIFT key or SHIFT LOCK key and any of the alphanumeric keys letter or number an upper case character prints a Repeat Keys When you press and hold the SPACE BACKSPACE RETURN LINE FEED or _ keys the code automatically repeats b Special Keys Control CTRL Escape ESC LINE FEED and...

Page 189: ...s see Table A I in Appendix A ESC The Escape key also generates a special function or machine action when used with another key For exam ple pressing ESC and M or m at the same time sets the left margin Table A 2 lists addi tional functions performed with the ESC key Similarly using the ESC key with other keys sets hori zontal tabulations Table A 3 and vertical tabulations Table A 4 To vary spacin...

Page 190: ...ey pad inputs numeric data Do the SHIFT and CTRL keys when inputting numerical data you locate your position on the numeric pad the number raised piece 2 2 3 Control Section The control section includes the following keys a LOCAL Remote not use To help S has a Press this key to enter the local mode the key auto matically locks In local mode the SPINWRITER oper ates as a typewriter When you release...

Page 191: ...ll the way forward for a single copy and all the way rearward for an original and five carbon copies Intermediate posi tions provide for form thicknesses between these two extremes When printing on a form of several copies with this lever moved toward the rear you may have to increase the print hammer intensity for optimum print quality by changing the impression control switch see Figure 2 4 9 3 ...

Page 192: ...RIBBON SELECTOR SWITCH I MPRESS ION CONTROL SWITCH BLACK OR MULTI RED BLACK STRIKE RIBBON RIBBON Figure 2 4 Printer Controls H M L ...

Page 193: ... printing on a friction feed platen to ensure proper feeding of the paper PLACE IT FORWARD WHEN PRINTING ON A PIN FEED PLATEN OR WHEN USING A FORMS TRACTOR ASSEMBLY 9 Impression control switch This three position switch located under the top cover controls the printing impression You may set this switch as follows L low for mInImum impact pressure which may be re quired for small typefaces 12 pitc...

Page 194: ...PAPER GUIDE V Figure 2 5 Rear Paper Feed Path FEEDTHRU Figure 2 6 Bottom Paper Feed Path Optional Feature 2 11 ...

Page 195: ... form position 1 Adjust copy control lever Place this lever in extreme forward position for a single copy and adjust it grad ually toward rear as the number of copies increases m Lower the paper guide and silencer hood 2 4 2 Pin Feed Paper Loading a Raise paper guide and silencer hood b Move the pressure bail away from the platen c Pull paper release lever forward it must REMAIN in the FORWARD pos...

Page 196: ...n right tractor with paper feed holes You may have to move the tractor assemblies to do this Release the locking knobs and slide the assemblies to the desired position i Push in and rotate the right knob of the platen to position the paper to the first line position j Lower the paper guide and the silencer hood 2 5 SPINWRITER PREPARATION NOTE Before you apply power to the SPINWRITER make sure that...

Page 197: ...ng a commun ication link The SP swi tch is set according to the type of printing thimble used 2 7 SELF TEST MODE SPINWRITER models have a built in self test program which give you a repeated printout of alphanumerics and symbols Figure 2 7 shows a typical test pattern printout Press the FORM LENGTH switches see Table 2 1 to vary the column width and line spacing of the printout In the Test Mode wi...

Page 198: ...own fox jumps over the lazy dog Il I THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 123 456 7890 X The quick brown fox jumps over the lazy dog 1 en THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 123 456 7890 X The quick brown fox jumps over the lazy dog I I I THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG 123 456 7890 X The quick brown fox jumps over the lazy dog THE QUICK BROWN FOX JUMPS OVER THE LAZY DOG...

Page 199: ...und CAUSE Power Source Cover Open Ribbon End Paper Out Carriage is in extreme left or right position Ribbon broken or not installed properly Thimble broken or not installed properly Broken carriage cable Obstruction in path of carriage 2 16 CORRECTIVE ACTION 1 Is SPINWRITER con nected to ac power 2 Is POWER switch in ON position 1 Is cover closed tightly 2 Check ribbon car tridge If using a multi ...

Page 200: ...y Damaged platen or thimble REMOTE OPERATIONS Parity or framing error Check condition No data input CORRECTIVE ACTION 1 Check paper load ing 2 Adjust tractors 3 Check paper release lever see 2 3 1 Replace if neces sary see 3 2 3 3 2 Check installation 1 Check position of copy control see 2 3 2 Check switch setting 3 Inspect for mars and or abrasions Replace if neces sary 1 Check PARITY and SPEED s...

Page 201: ...print image sharpest characters and maximum black and white contrast Select the proper copy control lever setting all the way forward for single copy and moved rearward as neces sary for additional copies Set the impression control switch for the best print image low for small typefaces 12 pitch medium for normal impact pressure and high for large typefaces or multiple copies Set the space pitch s...

Page 202: ...n is being used see Figure 3 2 f Press the ribbon cartridge downward until the locking tabs engage NOTE It may be necessary to rotate the manual feed knob on the cartridge in the direc tior indicated by the arrow to ensure proper seating g Check tension on the ribbon see step c h Close the top cover and restore ac power 3 3 PRINT THIMBLE REPLACEMENT The print thimble may be replaced as follows a T...

Page 203: ...CARD HOLDER BRACKET MANUAL FEED KNOB Figure 3 1 Ribbon Cartridge Removal LOCK PIECE ALIGNMENT HOLE AND STUD A Figure 3 2 Print Thimble Removal 3 3 ...

Page 204: ...ore ac power 3 4 FRICTION FEED ASSEMBLY REMOVAL If this option is installed it can be removed in the following manner a Turn POWER off and raise the top cover b Move the pressure bail away from the platen c Press the lock assembly upward shown in Figure levers and simultaneously raise the and toward the rear of the pr inter as 3 3 d Close the cover and restore ac power 3 5 FORMS TRACTOR ASSEMBLY R...

Page 205: ... LOCKING LEVER LOCK FRICTION LEVER FEED lIATTACHMENT PLATEN GROOVE PRESSURE BAIL Figure 3 3 Friction Feed Attachment Removal Right Side Only Figure 3 4 Forms Tractor Assembly Removal 3 5 LOCKING LEVER ...

Page 206: ... the platen c Press the locking tabs and lift the platen from the printer Figure 3 5 d Insert the replacement platen into position aligning the platen gear with the line feed idle gear Press the locking tabs and press the platen downward until it locks in place e Close the top cover and restore ac power PLATEN LOCKING TAB Figure 3 5 Pin Feed Platen Removal 3 6 ...

Page 207: ... 3 6 d Insert the replacement platen into position aligning the platen gear with the line feed idle gear NOTE Because it is possible to install the platen backwards be sure that the widest gear is on the right as the platen is installed from the front e Grasp the platen knobs press the locking tabs and press platen downward until it locks into place f Close the top cover and restore ac power LOCKI...

Page 208: ...Carriage Return N or n SO Shift Out a or 0 SI Shift In p or p DT E Data Link Escape Q or q DC 1 Device Control 1 R or r DC 2 Device Control 2 S or s DC 3 Device Control 3 T or t DC 4 Device Control 4 U or u NAK Negative Acknowledge V or v SYN Synchronous Idle W or w ETB End of Transmission Block X or x CAN Cancel Y or y EM End of Medium Z or z SUB Substitute underline US Unit Separator or 1 ESC Es...

Page 209: ...ht Margin Set FF Length Set Left Margin Reset Left Margin Tables A 3 through A 5 list additional ESC functions for Models 5510 5520 Examples To set the left margin press the following keys in this order 1st key 2nd key ESC M or m You can set FORM FEED FF length from the keyboard or from a remote location by using the ESC keys as follows 1 ESC L or 1 2 ESC These actions load the number of line feed...

Page 210: ... 151 G W G W G W G W G W 8 24 40 56 72 88 104 120 136 152 H X H X H X H X H X 9 25 41 57 73 89 105 121 137 153 y y y y y 10 26 42 58 74 90 106 122 138 154 J Z J Z J Z J Z J Z 11 27 43 59 75 91 107 123 139 155 K K K K K 12 28 44 60 76 92 108 124 140 156 L L L L L 13 29 45 61 77 93 109 125 141 157 M M M M M N I N A N 1 N A 15 31 47 63 79 95 11 127 14 30 46 62 78 94 10 126 o 16 32 o 48 64 o 80 96 o 1...

Page 211: ... Y X X X I X X y I IXX IXIY X IXX IXy X X X X X X X X X X X X X X IXr X X X X X X IxX X X X X X X I X X X X X X IXX X h X X X X I Example TAB POS ITI ON To tab to a vertical position 26 lines before the preset line reverse press the following keys in this order 1st key ESC 2nd key X or x 3rd key Z or z A 4 ...

Page 212: ... 6 120 V 7 48 G 7 120 W 8 48 1 61 H 8 120 X 9 48 I 9 120 Y 10 48 J 10 120 1 12 Z 11 48 K 11 120 12 48 L 12 120 1 101 13 48 M 13 120 J 14 48 N 14 120 A 15 48 0 15 120 16 48 Examples 1 To space character s 12 120 inch apar t press the fol lowing keys in this order 1st ESC 2nd 3rd L or 1 2 To space lines 6 4S inch apart S lines inch press the following keys in this order 1st ESC 2nd 3rd U A 5 ...

Page 213: ...T DC4 4 D T d t 0 1 0 1 5 ENQ NAK 5 E U e u 0 1 1 0 6 ACK SYN 6 F V f v 0 1 1 1 7 BEL ETB 7 G W 9 w 1 0 0 0 a BS CAN I a H x h x 1 0 0 1 9 HT EM I 9 I Y i y 1 0 1 0 10 LF sua J Z j z 1 0 1 1 11 VT ESC K k 1 1 0 0 12 FF FS L I I I 1 1 0 1 13 CR GS 0 M J m 1 1 1 0 14 SO RS N n 1 1 _1 1 15 SI US 0 0 DEL See Table A l for definitions of ASCII code NOTE Both c r lumn 4 and 5 capital letter SI and colum...

Page 214: ...ab Stop Set Left Margin Set Right Margin Print in Red Print in Black Negative Half Line Feed Half Line Feed Negative Line Feed Absolute Horizontal Tab Absolute Vertical Tab Define Vertical Motion Index VMI Define Horizontal Motion Index HMI 1 To set left margin press the following keys in this order 1st key ESC 2nd key 9 2 To set absolute vertical tab at 52 the following 3 key ESC sequence is used...

Page 215: ...eys CTRL with 3rd key 6 see Table B 2 see Table B 3 6 To set Graphics use the ESC 3 key to Reset use ESC 4 While in the Graphics mode carriage movement is com pletely separated from printing i e printing a character does not automatically move the carriage The carriage is moved only by executing a tab space carriage return or backspace operation The tab commands operate the same as they do in Norm...

Page 216: ...DCl 11 q 71 Q 51 ETB 17 w 77 W 57 ENQ 05 e 65 E 45 DC2 12 r 72 R 52 DC4 14 t 74 T 54 EM 19 y 79 Y 59 NAJ 15 u 75 U 55 HT 09 i 69 I 49 SI OF 0 6F 0 4F OLE 10 P 70 P 50 ESC IB 5B J 50 FS lC SC I 7C LP OA LF OA LF OA CTRL 01 LOCK SOH a 61 A 41 DC3 13 s 73 S 53 EDT 04 d 64 0 ACK 06 f 66 F 46 BEL 07 67 G 47 g BS 08 h 68 H 48 LF OA J 6A J 4A VT DB k 6B K 4B FF OC 1 6c L 4C 3B 3B 3A 27 22 27 GS ID 7B 70 ...

Page 217: ...X EOT ENG ACK 8EL BS HT 10 LF VT FF CR SO SI DLE DCl DC2 DC3 20 DC4 NAK SYN ETB CAN EM SUB ESC FS GS 30 RS US SP I 11 40 I I 0 1 50 2 3 4 5 6 7 8 9 60 A 8 C D E 70 F G H I J K L M N 0 80 P G R S T U V W X Y 90 Z I I A a b c 100 d e f 9 h I j k I m 110 n 0 p q r s t u v w 120 x y z I I f B 4 ...

Page 218: ...aracter buffer can accept it A set or style of alphabet ie numer ie and special characters symbols A device for aligning and feeding con tinuous forms through the printer Data is transmitted to the SPINWRITER in an incorrect format an error will result from an incorrect baud rate set ting or the wrong number of internally programmed start and stop bits An internally programmed computer check ing m...

Page 219: ... USER S COMMENTS FORM Document SPINWRITER Tennina1s Operator s Guide Document No 10003 01 Please suggest improvements to this manual u Please list any errors in this manual Specify by page a From Name Title _ Company _ Address _ Date ...

Page 220: ...Y CARD FIRST CLASS PER MIT NO 386 LEXINGTON MA POSTAGE WILL BE PAID BY ADDRESSEE NEe Information Systems Inc Dept Publications 5 Militia Drive Lexington MA 02173 FOLD HERE Seal or tape all edges for mailing do not use staples Nn P S t ClF 1 NECFSSAQy WMA Lf f IN THF UNITFr1 STI TfS _ 1 ...

Page 221: ......

Page 222: ...ck Accessing 1 3 1 1 3 2 1 3 2 1 1 3 3 Actuator Control logic Figure 21 1 3 3 1 Power On Reset 1 3 3 2 Forward Seek 1 3 3 3 Reverse Seek 1 3 4 Track Zero Indicator 1 4 0 Read Write Operations 1 4 1 1 4 2 1 4 3 1 4 4 1 4 5 1 5 0 Read Write Head 1 5 1 1 5 2 1 5 3 1 5 4 1 6 0 Write Current Operation Figure 32 1 6 1 1 6 2 1 6 3 1 6 4 1 7 0 Read Circuit Operation Figure 33 1 7 1 1 7 2 1 7 3 1 8 0 Inter...

Page 223: ...Protect Detector 31 2 4 5 1 Write Protect Detector Removal and Installation 31 2 4 5 2 Write Protect Detector Adjustment 31 2 4 6 Head Load Mechanism Assembly 32 2 4 6 1 Head Load Mechanism Removal and Installation 32 2 4 6 2 Head Load Mechanism Adjustment 32 2 4 7 Index Sector Photo Transistor Assembly 34 2 4 7 1 Index Sector Photo Transistor Assembly Removal and Installation 34 2 4 7 2 Index Sec...

Page 224: ...ress Mark 11 21 Activator Control Logic 15 22 CountO 16 23 Count 1 16 24 Count 2 16 25 Count 3 16 26 Byte 17 27 Basic R W Head 18 28 Recorded Bit 18 29 Reading a Bit 18 30 1F and 2F Recording Flux and Pulse Relationship 19 31 Read Write Heads 19 32 Write Circuit Functional Diagram 20 33 Read Circuit Functional Diagram 21 34 Data Separation Timing Diagram 22 35 Interface Connections 23 36 Interface...

Page 225: ...48 Azimuth Burst Patterns 45 FlowCharts 47 Logic Diagrams 53 Physical Locations 57 49 1 012 61 49 2012 62 Illustrated Parts Catalog 63 M 67 Schematic Diagrams 68 ...

Page 226: ... Driver 3 Head Load Solenoid Driver 4 Read Write Amplifier and Transition Detector 5 Data Clock Separation Circuits SA851 6 Write Protect 7 Drive Ready Detector Circuit 8 Drive Select Circuits 9 Side Select Circuit 10 In Use and Door Lock Circuits 11 Write Current Switching Read Compensation 1 1 1 HEAD POSITIONING The read write heads are accurately positioned by a Fasflex metal band stepping moto...

Page 227: ...tio and insures diskette interchangeability The read write heads are mounted on a carriage which is positioned by the Fasflex actuator The head carriage assembly utilizes a combination f1exured rigid head mounting system This allows the flexured head to load the media against its rigidly mounted counterpart see Figure 2 The diskette is held in a plane perpendicular to the readlwrite head by a pta ...

Page 228: ... referring to serial data being written onto or read from the disk drive is defined as eight 8 consecutive bit cells The most significant bit cell is defined as bit cell 0 and the least significant bit cell is defined as bit cell 7 When reference is made to a specific data bit Le data bit 3 it is with repsect to the corresponding bit cell bit cell 3 During a write operation bit cell 0 of each byte...

Page 229: ...es using FM encoding can be achieved by us ing The SA850 851 diskette drive with its proprietary ceramicJferrite read write head Phase locked loop VFO data separator Write precompensation Provision of the phase locked loop data separator and write precompensation circuitry is the responsibility of the user of the SA850 851 diskette drive Shugart Associates will provide design information as requir...

Page 230: ...bits at the leading edge of the bit cell if 1 There is no data bit or clock bit written in the previous bit cell and 2 There will be not data bit written in the present bit cell NOTE In M2FM MFM the write oscillator frequency is doubled while maintaining the same flux changes per inch as FM Thus the bit cell in M2FM MFM is Y2 that in FM Data transfer rate is also doubled since a 1 to 1 relationshi...

Page 231: ...is Format the using system may record up to 32 sectors records per track Each track is started by a physical index pulse and each sector is started by a physical sector pulse This type of recording is called hard sectoring Figure 8 shows a typical Sector Recording Format for 1 of 32 sectors 1 400 S 200Its SECTOR Ir WRITE URN OFF 1 CLOCK I DATA CLOCK I l I DATA IDENTIFIER ITS 40 BITS MAX 112 BITS 7...

Page 232: ...Y 10 SECTOR DATA CRC CRC ADDRESS TRACK SIDE SECTOR CRC CRC ADORES USER DATA 1 2 MARK ADDRESS NUMBER NUMBER LENGTH 1 2 MARK I LHEX 00 FOR SIDE 0 HEX 01 FOR SIDE 1 HEX 00 FOR 126 BYTe SECTORS 5 9 I I J FM MFM 11 22 6 12 o 3 BYTES BYTES FM MFM D I IA1 I 26 6 0 53 12 3 BYTES BYTES FIGURE 9 TRACK FORMAT Note byle counl is tor 26 records Gap 3 change byte counl with record length ...

Page 233: ...ATE WRITE ill 3b C2 dclck P lt 14 llJ 3 bY_ A1 dclcl AlII _ DA II TradI numtJet head sector fecm t letJgth GeNr bV CRC _0 _idl be 1aCCITT VHl l J 1 b IW of FB or Fe FIGURE 10 MFM TRACK FORMAT COMPARISON BIT CELL 1 BIT CELL 2 BIT CEll 3 BIT CEll 4 an CEllS BIT CEll 6 BIT CELL J C D C D D C D D C D C C BIT CELL 0 f NDEX ADDRESS MARK BYT I BINARY REPRESENTATION OF DATA BITS ClOCK BITS o o o HEXADECIM...

Page 234: ... B T CHl 7 UT CEll e oT cm I I oT cm 1 C LL I oT C l l C LL S oT C E l l C E l l 1 CElLO I 1 DATA ACDRUS At BYTE 1 BINARY REPRESENTATION OF DATA BITS CLOCK BITS o o o o HEXADECIMAL REPRESENTATION OF DATA BITS FB CLOCK BITS C7 FIGURE 13 DATA ADDRESS MARK FM DELETED 0 fA AODRESS MARl BYTE l BINARY REPRESENTATION OF DATA BITS CLOCK BITS o o o o o o HEXADECIMAL REPRESENTATION OF DATA BITS FB CLOCK BIT...

Page 235: ...o D o o o BIT ELL I BIT CELL IBIT CELL IBIT CELL IBIT CELL 2 3 4 5 BIT CELL 7 1 _ MFM 10 ADDRESS MARK e HEXADECIMAL REPRESENTATION OF BINARY REPRESENTATION OF DATA BITS CLOCK BITS o o o o o o o o o FE 00 FIGURE 16 MFM ID ADDRESS MARK D D D D D o D BIT CELL 7 BIT ELL IBIT ELL IBIT ELL I 1 DATA ADDRESS MARK l HEXIOECIMAL REPRESENTATION OF FB BINARY REPRESENTATION OF DATA BITS CLOCK BITS o o o o o o ...

Page 236: ...A ADDRESS MARK D D C C D 1 PRE INDEX ADDRESS MARK I BIT ELL IBIT ELL I BIT CELL 7 BINARY REPRESENTATION OF HEXIDECIMAL REPRESENTATION OF DATA BITS CLOCK BITS o o o o o o o o o o o C2 14 FIGURE 19 MFM INDEX PRE ADDRESS MARK C D D C D Sl n n__ Jn__1L BIT CELL o BIT CELL IBIT CELL 3 4 BIT CELL 7 PRE ADDRESS MARK HEXIDECIMAL REPRESENTATION OF Al BINARY REPRESENTATION OF DATA BITS CLOCK BITS o o o o o ...

Page 237: ...ress Mark FM is a unique byle to identily the 10 field and not written per the en code rules ReIer to Figure 12 10 Address Mark MFM is one byle 01 FE and it is writlen per the encode rules ReIer to Figure 16 Gap 2 10 is a lour byle address containing track number hear number record number and record length CRC is two byles lor cyclic redundancy check Gap lrom IDGRG to data AM sync and allows lor s...

Page 238: ...1 3 2 1 There are four stator poles with four teeth per pole extending axially the length of the rotor The rotor contains 25 teeth per half spaced 14 4 degrees apart with each being displaced one tooth pitch relative to each other The rotor is permanently magnetized with one gear half being the north pole and the other the south pole The four winding per phase are those which when energized will m...

Page 239: ... reverse direction five tracks Assuming Present position of the read write heads to be track 05 Direction Select at a positive level from the host system Write Gate inactive Five step pulses to be received FF A is off and FF B is on drivers 1 and 3 active Plus Direction Select is inverted and becomes Direction Select With FF A off and FF B on lows are presented to Exclusive ORs A and B With the fi...

Page 240: ...CTION 0 0 t SELECT FFA c 0 I DRIVER 3 JIB 0 0 116 FF l _c 0 DRIVER 4 t V sTEP r READ GAfF 1 TP27 POWER ON RESET DRV SELINT TRACK 00 DETECT TP26 42 ll TRAC 00 TRKOO PHASE A _I PHASE B TRACK STEP COUNT 00 o 0 1 02 3 03 04 05 06 07 2 0 3 2 08 09 o 1 10 11 3 2 FIGURE 21 ACTIVATOR CONTROL LOGIC 15 ...

Page 241: ... A2 A1 A2 A1 2 2 FIGURE 22 COUNT a FIGURE 23 COUNT 1 A2 Al A2 Al 2 2 FIGURE 24 COUNT 2 FIGURE 25 COUNT 3 ...

Page 242: ...tion a bit is recorded when the flux direction in the ring is reversed by rapidly reversing the current coil The fringe flux is reversed in the gap and hence the portion of the flux flowing through the oxide recording surface is reversed If the flux reversal is instantaneous in comparison to the motion of the diskette it can be seen that the portion of the diskette surface that just passed under t...

Page 243: ... RECORDING SURFACE I MYLAR l BASE FIGURE 27 BASIC R W HEAD DISKETIE MOTION CURRENT I RECORDED BIT FIGURE 28 RECORDED BIT DISKETIE MOTION VOLTAGE PULSE FLUX REVERSAL IN GAP RECORDED BIT FIGURE 29 READING A BIT 18 DISKETTE MOTION ...

Page 244: ...ead write head This will cause a change in the flux pattern for each bit The current through either of the read write coils will cause the old data to be erased as new data is recorded 1 5 4 On a read operation as the direction at flux changes on the diskette surface as it passes under the gap current will be induced into one of the windings of the read write head This will result in a voltage out...

Page 245: ...tem and not Write Protect are anded together to provide write current 1 6 3 The output of one of the Write Drivers allows write current to flow through one half of the read write coil of each head When the Write Data Trigger toggles the other Write Driver provides the write current to the other half one the read write coits 1 6 4 When write current is sensed flowing to the Write Drivers a signal i...

Page 246: ...al is fed to the amplifier section of the read circuit After amplification the read signal is fed to a filter where noise spikes are removed The read signal is then fed to the differential amplifier 1 7 2 Since a pulse occurs at least once every 41 S and when data bits are present once every 21 s the frequency of the read data varies The read signal amplitude decreases as the frequency increases N...

Page 247: ...r to Figure 35 1 8 2 AC POWER REFER TO TABLE 1 The AC power to the drive is via the connector P4 J4 located to the rear of the drive and below the AC motor capacitor The P4 J4 pin designations are outlined in Table 1 for standard as well as optional AC power 1 8 3 DC POWER REFER TO TABLE 2 DC power to the drive is via connector P5IJ5 located on the non component side of the PCB near the P4 con nec...

Page 248: ... DRIVE SELECT 4 SIDE SELECT OPT 32 3 DIRECTION SELl CT SIDE SELECT OPT 33 14 STEP 35 3 WRITE DATA 3 37 WRITE GATE 40 3 TRACK 00 42 41 WAnE PROTECT 44 43 READ DATA 4 45 SEP DATA 851 ONLY 4 47 SEP CLOCK 851 ONlYl 50 4 5 VOC 5 J5 1 6 5 V RETURN J DCGND 24 voe 24 V RETURN 1 2 ACINPUT J4 1 FRAME GROUND ACGND n AC INPUT FAAMEGND gTWISTED PAIR These lines are alternate inpul oulput lines and they are ena...

Page 249: ... 127 V Rtn 170 253 V Rtn MAX 0 35 Amps 0 25 Amps 0 35 Amps 0 25 Amps CURRENT FREQ 0 5 Hz 0 5 Hz TOLERANCE TABLE I P5 DC VOLTAGE TOLERANCE CURRENT MAX PIN RIPPLE p to p 1 24 VDC 2 4 VDC 1 0A Max 100 mv 0 85A Typ 2 24 V Return 6 5 V Return 5 5 VDC 0 25 VDC 1 1A Max 50 mv 1 0A Typ 611 either customer inslallable oplion described in sections 7 1 and 7 3 are used Ihe currenl require men for the 24 VDC ...

Page 250: ...erciser is designed to enable the user to make all adjustments and check outs required on the SA850 851 drives when used with the SA122 Alignment Diskette The exerciser has no intetligent data handling capabilities but can write both 1f and 2f frequencies The exer ciser can enable read in the drive to allow checking of read back signals 2 1 3 SPECIAL TOOLS The following specials tools are availabl...

Page 251: ...a is not recovered the error is not recoverable 2 2 3 WRITE ERROR II an error occurs during a write operation it will be detected on the next revolution by doing a read opera tion commonly called a write check To correct the error another write and write check operation must be done II the write operation is not successful after ten 10 allempts have been made a read operation should be attempted o...

Page 252: ...CTORS 2 2 7 1 J1 P1 provide the signal interface to the host system The pin designators are as listed below 2 Write Current Switch 4 Alternate I O 6 Alternate 110 8 Alternate 1 0 10 Two Sided optional 12 Disk Change optional 14 Side Select 16 In Use optional 18 Head Load optional 20 Index 21 Ready 24 Sector 851 only 26 Drive Select 1 or Side Select Option 28 Drive Select 2 or Side Select Option 30...

Page 253: ... IndexiSector 1 Detector R Key S Stpr WndgJRes A T Stpr Wndg Res B U Head Load 1 Key 2 Ground 3 Ground 4 Ground 5 Ground 6 Ground 7 Not Used 8 Not Used g 24V Door Lock 10 5V Track 00 Detector 11 5V Write Protect 12 5V Index 0 1 Detector 13 Not Used 14 Key 15 Stpr Res A 16 Stpr Res B 17 24V Head Load 2 2 7 3 J3IP3 J3IP3 provides to interface to the ReadlWrite coils and the trim erase coils of the m...

Page 254: ...time it is unnecessary Visual inspection is the first step in every scheduled maintenance operation Always look for corrosion dirt wear binds and loose connections Noticing these items during PM may save downtime later Remember do not do more than recommended preventative maintenance on equipment that is operating satisfactorily 2 3 2 PREVENTIVE MAINTENANCE PROCEUDRES Details of preventative maint...

Page 255: ... destroy the alignment and the actuator assembly will have to be returned to the factory for alignment 2 4 0 REMOVALS ADJUSTMENTS NOTE Read the entire procedure before attempting a removal and or adjustment 2 4 1 MOTOR DRIVE 2 4 1 1 DRIVE MOTOR ASSEMBLY REMOVAL AND INSTALLATION a Extract 3 contacts to disconnect motor from AC connector J4 b Loosen two screws holding capacitor clamp to the base Rem...

Page 256: ...erminals solder joints Remove the screw holding the LED assembly to the cartridge guide Reverse the procedure for installation Check index timing and readjust if necessary Refer to Section 2 4 7 2 2 4 5 WRITE PROTECT DETECTOR 2 4 5 1 WRITE PROTECT DETECTOR REMOVAL AND INSTALLATION a Remove connectors from PCB and remove PCB b Extract wires from P2 connector pins 4 0 11 and M c Remove cable clamps ...

Page 257: ...e head a couples of times and reverify the clearance required c Step to track 76 and load the head check the clearance between the bail and the lift tab Lift tab must not be in contact with the bail and clearance must be a minimum of 008 and no greater than 03Z d Return to track 00 1 Sync oscilloscope on TP 11 Head Load Set time base to 10 msecldivision Connect one probe to TPl and the other to TP...

Page 258: ... LOADER SPRING ADJUSTMENT PLATE BAIL ADJUSTMENT SCREW BAIL AND LIFT TAB CLEARANCE Z8 020 012 FIGURE 37 HEAD LOAD MECHANISM ADJUSTMENT FIGURE 38 HEAD LOAD TIMING 33 ...

Page 259: ...sweep and the first data pulse This should be 200 100 sec If the timing is not within tolerance continue on with the adjustment f loosen the holding screw in the Index Transducer until the transducer is just able to be moved g Observing the timing adjust the transducer until the timing is 200 100 sec Insure that the transducer assembly is against the registration surface on the base casting h Tigh...

Page 260: ...E ADJUSTMENT a Insert the shoulder screw tool PIN 50377 1 through the adjustment hole in the cartridge guide and screw completely into the base casting hand tight b Move the handle into the latched position and hold lightly against the latch c Tighten two screws holding the cartridge guide to the latch plate d Remove the tool and check to determine if the flange on the clamp hub clears the cartrid...

Page 261: ...is tried and the output is still low it will be necessary to install a new head and actuator assembly 2 4 10 1 HEAD ACTUATOR ASSEMBLY REMOVAL AND INSTALLATION a Remove the connectors and the PCB b Remove cabie clamp holding R W head cable on PCB side of drive c Remove the grommet from the cable bracket on head side d Unload heads Refer to Section 2 4 3 Steps D E e Remove the two or four screws hol...

Page 262: ...a The tools necessary to perform this alignment procedure will consist of penetration gauge tool set screwdriver and A nut driver see Figure 39 TOOL MASTER DIAL INDICATOR pPLATE SCREWDRIVER 4 NUT DRIVER FIGURE 39 HEAD PENETRATION TOOLS 37 ...

Page 263: ...ke sure it s indicating surfaces are clean and properly set long hand on zero and small hand on three while it s resting on the penetration tool master See Figure 40 NOTE When the tool is not being used it should be kept where it won t be dropped or knocked off the work bench FIGURE 40 DIAL INDICATOR ...

Page 264: ...irst and counfer bore side up Slide the plate up and over the spindle until iI s squarely over the spindle and close the door See Figure 41 NOTE The penetration plate is made of harden tool steel and care should be used not to damage spindle or any other part of the drive during insertion of extraction FIGURE 41 PENETRATION PLATE INSTALLATION 39 ...

Page 265: ...tration plate until you feel the block snap into place See Figure 42 NOTE Make sure all surfaces are clean the block is squarely and fUlly snapped onto the plate Also avoid handling the block by the indicator FIGURE 42 DIAL INDICATOR INSTALLATION 40 ...

Page 266: ...o head as shown in Figure 43 L Check the dial indicator for the proper selling The long hand should be between 3 and 3 with the short hand pointing at three If penetration setting is out ot this range then continue with pro cedure starting at step 7 See Figure 44 INDICATION TAB FIGURE 43 INSTALLATION CHECK GAUGE POINT FIGURE 44 CORRECT PENETRATION 41 ...

Page 267: ... on the left side of three the HAC assembly must go to the right B If small hand is on the right side of three the HAC assembly must go to the left j When penetration is set tighten the two or four mounting screws using a nut driver k As you tighten the two mounting screws make sure the HAC casting is flush making contact with the machined lip on the base casting I Check penetration gauge again to...

Page 268: ...the adjustment by stepping off track and returning Check in both directions and readjust as required Whenever the Head Radial Alignment has been adjusted the Track 00 detector adjustment must be checked Section 2 4 11 2 NOTE Alignment diskette should be at room conditions for at least 1 hour before alignment checks Steps the heads to track 38 Sync the oscilloscope external negative on TP12 Index S...

Page 269: ...OF LEFT 3 MIL OFF TRACK TOWARD 76 J FIGURE 46 HEAD RADIAL ALIGNMENT FIGURE 47 MOTOR PLATE 2 4 11 DOOR LOCK SOLENOID AND IN USE LED ASSEMBLY REMOVAL a Perform steps 2 4 12a and 2 4 12h b Remove door lock assembly c Reverse procedure to install new assembly d Adjust of the door lock should not be necessary If it has to be the gap between the armature tab and the latch should be 015 010 This adjustme...

Page 270: ...0 18 I 12 12 18 FIGURE 48 AZIMUTH BURST PATTERNS 45 ...

Page 271: ...go low Adjust the detector assembly towards the actuator assembly if not low e Check the adjustment by stepping the heads between tracks 00 and 02 observing that TP26 is low at track 02 and high at track 00 A perfect adjustment is if you have a square wave on a scope 2 4 13 FRONT PLATE ASSEMBLY REMOVAL a Insert the cartridge guide adjustment tool PIN 50377 1 through the adjustment hole in the car ...

Page 272: ...Flow Charts ...

Page 273: ...TART Insert Diskette with Write Protect Slot Uncovered Perform Write Protect Assembly Adj Para 2 4 5 2 YES Insert Diskette with Write Protect Slot Covered END YES 47 NO Replace Write Protect Assembly Para 2 4 5 1 Replace Drive PCB ...

Page 274: ...Check logic Level at TP11 Check Logic Level at 3A Pin 3 Replace Drive PCB HEAD LOAD INOPERATIVE Check Logic Level at 5C Pin 3 Check Door Close Switch tor Loose Wire and Insure Closure NO END Check I O Cable or Controller Replace Door Switch NO END ...

Page 275: ...gic Level at TP26 Low Replace Track 00 Assembly Para 2 4 1 22 Replace Drive PCB YES Step to Track 02 Check Logic Level TP26 Return Track 00 Flag to its Rest Position at Track 00 Stop Perform Track 00 Assembly Adj Para 2 4 12 2 YES Step to Track 00 Check Logic Level TP26 NO 49 ...

Page 276: ...oard for DC Voltage END Check Power Source Install Jumper Install Jumpers NO Replace Drive PCB Check 10 Cable or NO Controller Check YES Drive Select Jumper Check Terminator 5E 1500hm Install Terminator Replace 110 Cable Controller 50 ...

Page 277: ... Check AC Voltage at Drive Motor Connector J4 Check Drive Motor for Rotation Check Drive Belt NO Replace AC Drive Motor Para 2 4 1 Check AC Power Source END Check Cartridge Guide Adjustment Para 2 4 9 2 Replace Drive Belt END 51 ...

Page 278: ...nd Connector at J4 Replace AC Drive Molor Para 2 4 1 NO Check Diskette Rotation Replace Index Sector Phototransislor Assembly Para 2 4 7 Perform Index Sector Adjustment Para 2 4 7 2 END 52 Turn Diskette Over Re insert Check TP13 for Pulse 167 66 Msec END Check TPI for Pulse 167 66 Msec Replace Drive PCB ...

Page 279: ... Logic Diagrams ...

Page 280: ... I e 4 c I y DOOR LOCK ORNE SEL INT 2S lOW TWOSloeo I L I 0 IOPTiONAL OUTPUll l __ _t I cOC o t i 2 DISK CHANGE c a Y OPTIONAL OUTPUTI DRIVE SEl INT ICQ R c f TWO PULSE DETECTOR fOl T I F II 5V Y D I 5V v 5 1 M OOORo OSED W H _ 18 C HEAD LOAO V I O _ __ J 5V ln 90 III USE V POWER ON RESET J DIRECTION S E L E C T o 14 51 5V Ti I vt 5 0 I DRIVE SEL I S3726 asO IT 9 I DOOR CLOSED I I POWER ON ISlDE t...

Page 281: ...24V 24VlHEAD LOAD o SV w W WRITE PROT LED DETECT TRK 00 rv 44 Ino _ I Y DRIVE SELINT W WRITE PROTECT TPS TP6 o TP7 TP28 24V I 4 GND WRITE PROT INDEXLED 0 TP 10 GND lNDEXI TRKooLED GND TRK 00 6 GND TO DOOR CLOSED W NOTES rn CONNECTOR SYMBOL REFERENCE 1 Jl 2 J2 S JS mALL ODD NUMBERED PINS ON Jl CONNECTOR ARE GROUND J ...

Page 282: ...DHEAD lOAD W BlK 17 0 24V TO SOLENOID W WHT HEAD lOAD SOLENOID 6 GND TO DOOR W ORG I DOOR I GRY F ceoS s w CLOSEO SW 000 CLOSEC I RED H DOOR CLOSED K NOTES j GND WHEN ACTIVE AND 24 WHEN INACTIVE lJ 115 OR 230 VAC ...

Page 283: ...5 ORG BLK 12 5V INDEX j TRK 00 LED C BLK TRACK 00 EE r J R E DU L GND TRK 00 3 BRN LED DET TRK 00 roR 10__ 5V TRK 00 WRITE PROT LED D BLK WRITE PROTECT EE l RE D 1 M GND WRITE PROT 4 BRN LED DET WRITE PROTECT _____ l OR G _ 11 __ 5V WR PROT G e I USE I N S OJ IN USE LED 2 BLK 6 NOTES OJ GND WHEN INACTIVE AND 1 5VDC WHEN ACTIVE J ...

Page 284: ... Physical Locations ...

Page 285: ... a o I u J Z Z o 0 L L 57 a o o u J z z o i ...

Page 286: ... ...

Page 287: ...DGE GUIDE ADJUSTMENT SCREWS INDEX SECTOR LEO HUB CLAMP PLATE HEAD LOAD MECHANISM MOTOR CAPACITOR HEAD ACTUATOR ASSEMBLY CARTRIDGE GUIDE ADJUSTMENT TOOL HOLE CARTRIDGE GUIDE DISK COVER EJECT Mt CHANISM DRIV MOTOR ...

Page 288: ...o w W J Im t 5 a o f Ow J J W J 2 0 a o ...

Page 289: ...Illustrated Parts Catalog ...

Page 290: ... r I N 61 o N 0 ...

Page 291: ...R ...

Page 292: ... SCREW 1 18 51063 GUIDE OPEN ASSEMBLY 1 19 51134 CARTRIDGE GUIDE ASSEMBLY SEE FIGURE 50 1 20 50167 PIVOT 1 20 50670 PIVOT RACK MOUNT 1 21 50168 BIAS SPRING 1 22 51198 SPINDLE 1 23 10801 FLANGED BEARING SPINDLE 1 24 17200 DOOR OPEN SWITCH 1 25 50559 DEFLECTOR 2 26 12013 SCREW 6 32 X 438 4 27 12032 SCREW 8 X 50 2 2 28 FRONT PLATE ASSEMBLY SEE FIGURE 51 29 11905 SCREW 2 30 50142 HANDLE 1 31 12011 SCR...

Page 293: ...13 12 11 14 FIGURE 50 1 4 2 ...

Page 294: ... 6 12015 SCREW 8 32 2 7 12020 SCREW 8 32 2 8 50546 PLATE HUB CLAMP 1 9 50254 HUB ASSEMBLY 1 10 50031 SPRING CLAMP 1 11 12016 SCREW 8 32 1 12 51029 LED ASSEMBLY 1 13 50151 LATCH 1 14 10187 SCREW 6 32 2 15 12015 SCREW 8 32 2 16 51061 STRIPPER TOP 1 17 50313 WRITE PROTECT ASSEMBLY 1 18 12026 SCREW 1 19 51176 HEAD LOAD MECHANISM 1 20 51075 LIMITER 1 21 10014 8 WASHER 1 22 12020 SCREW 8 32 1 65 ...

Page 295: ...1 2 FIGURE 51 66 7 ...

Page 296: ...TE LOCK 51043 FRONT PLATE ASSEMBLY LITE LOCK RACK MOUNT I 50587 PUSH BAR 1 2 50349 FRONT PLATE 1 50667 FRONT PLATE RACK MOUNT 1 3 51038 LATCH ASSEMBLY DOOR LOCK 1 4 10002 SOLENOID 1 5 12035 SCREW 4 40 X 250 2 6 50691 SPRING LATCH INTERLOCK 1 7 12013 SCREW 6 32 X 312 2 8 50183 BUMPER 1 67 ...

Page 297: ... Schematic Diagrams ...

Page 298: ...I 1 RPI 10 IT 3 6 Lf 8 RP2 3T 4 1Ii IO TPZ 9 J lf h n T 1 7L 4 P2 v j P l e 477OKOK TPZS b r o 8r 7 1 7 8 14i I RS I RPZ f c ISO 5 1 8 RPZ 7 S s 1 7c 1 JI I _ 1 3K v RS7 C 4701 i P WRm 1 ROr LED 2 t ISO I o A B c RSS 2 E lA IlZvJ ...

Page 299: ... l jl3A S J 5V 6 7 CoRle V 1 z_ y I r sD 3 I I 1 tz4V 3 1 400 1 77 W 4Af V 0 424 1 I eRn 2 _ j IJ oo 3 1 3 U 7 v lsw 5 i I 3B ROO t 13 2D 11 10 3 Q lB 1912D 8 5 1 i1J 4 71 S K 4F aSI l t J 4 5 en I 9 8 t4 ill 5 0 1 L J 10 5O O IzcQ 5 2S 4 I f41j3F b 0 10 l 4C QiZE e i L 41 i I br 11 I 20 t J Z 5 R 9 Z 2D 3 113 9 __ i R I R q 3F 8 7 10 22 I r RM 10 5N f IZ F I RS5 3 3E II F i 1_ 4 7K DC R ZI3F 3 0 ...

Page 300: ... Rb9 I IK 1 1 11 I IK I Zw lIZ I ZW 1 2 CR22 8D SVT 15 1 C 21 Ch3 R 6 8 l IZO I SE I CR9 IO v v v 7 V V 4 DE I CT ER S I IDE CT c BD B READ 66 TE A 4 pc POSITIOl 1 JNIJSE O S JI 5NDI 0 EU M N S P I f II _ I 5 1 7400 5D bE 7E bEl 2 0 11 12 O 1 7 7402 1 r 3C 74 C4 3B 4C 3Bh A 6 14 7 5 r r 51 7407 BD I c J C8S1 cq LO 21 21 74 Zl Sc 1 I 7 Z 917 4 30 3 3 3 C21 29 I 7432 2 r 14 I SOy 40 41 2 a 1 I 7438 ...

Page 301: ...1 7 i4 7 14 7 i4 7 R 7 1 14 7 i4 jZ FOR FM AfM NF 1 08 lv 2 FM t JOTE S Ul l SS O EP SE l tClI IE D l L c WI C i ORS AA l l MICROf P ADS 50 1 BO 20 2 ALL DIODES RE 4148 3 I LL IIJWC CRS RE 1 1 A ICl Dl c lR 6 0 70 4 l LL RE SIS OIlS AA 01 5 1 4 N 5 o SHOR II lG pt I S I lSTALL CI COI I lI c oR S I OL RtFER l c J J2 W J3W J4 Jr W Jro 0 0 IlJDIC cS c m IRKE OPTIOl l 8 0 c JOICI Y S JUMPl R oP OU 9 f...

Page 302: ...l Interface 4 1 Signal Interface 4 1 1 Input Lines 4 1 1 1 Input Line Termination 4 1 1 2 Drive Select 1 4 4 1 1 3 Side Select 4 1 1 4 Direction Select 4 1 1 5 Step 4 1 1 6 Write Gate 4 1 1 7 Write Data 4 1 1 8 Head Load Alternate Input 4 1 1 9 In Use Alternate Input 4 1 1 10 Write Current Switch Active Read Compensation 4 1 2 Output Lines 4 1 2 1 TrackOO 4 1 2 2 Index 4 12 3 Sector SA851 only 4 1...

Page 303: ...nate Input Activity LED 7 7 Write Protect Optional Use 7 8 Disk Change Optional Output 7 9 Side Selection Using Direction Select 7 10 Side Selection Using Drive Select 711 Door Lock Latch 7 12 Two Sided Optional Output 7 13 Head Current Switch Active Read Compensation 7 13 1 Head Current Switch 7 13 2 Active Read Filter 7 14 Ready Standard Ready Modified 7 15 Head Load Latch 8 0 Operation Procedur...

Page 304: ...Component Locations P N 25188 22 MLC 11 PCB Component Locations P N 25200 23 Select Drive Without Loading Head Circuit 24 Stepper Motor Enable Circuit 25 Load Head Without Selecting Drive or Enabling Stepper Circuit 26 Radial Ready Circuit 27 Radial Index Sector Circuit 28 In Use Activity LED Circuit 29 Write Protect Circuit 30 Disk Change Timing 31 Disk Change Circuit 32 Side Selection Using Dire...

Page 305: ......

Page 306: ... track to track access time In addition Shugart s Bi Compliant read write head assembly pro vides superior compliance resulting in excellent data integrity Other valuable features include programmable door lock and write protect plus dual index sensor to dif ferentiate between single and two sided diskettes The SAB50 B5l will prove highly cost effective in applications such as intelligent terminal...

Page 307: ... ms 15 ms 50 ms Double Density 1600 kilobytes 800 kilobytes 10 4 kilobytes 1000 kilobytes 500 kilobytes 6 66 kilobytes 500 kilobits sec 83 ms 3 ms 91 ms 15 ms 50 ms 1 2 2 FUNCTIONAL SPECIFICATIONS Single Density Double Density Rotational Speed 360 rpm 360 rpm Recording Density 3408 bpi 6816 bpi inside track Flux Density 6816 fci 6816 lci Track Density 48 tpi 48 tpi Cylinders 77 77 Tracks 154 154 H...

Page 308: ...ts 24VDC 10 1 0A Max 5VDC 5 1 lA Max Mechanical Dimensions exlusive of front panel SA850R 851 R SA850 851 Height 4 62 in 117 mm 4 62 in 117 mm Width 855 in 217 mm 950 in 241 mm Depth 14 25 in 362 mm 14 25 in 362 mm Heat Dissipation Typical Maximum BTU Hr 200 245 Watts 60 72 1 2 4 RELIABILITY SPECIFICATIONS MTBF MTIR Component Life Error Rates Soft Read Errors Hard Read Errors Seek Errors Media Lif...

Page 309: ...id Driver 4 Read Write Amplifier and Transition Detector 5 Data Clock Separation Circuits SA851 only 6 Write Protect 7 Drive Ready Detector Circuit 8 Drive Select Circuits 9 Side Select Circuit 10 In Use and Door Lock Circuits 11 Write Current Switching Read Compensation 2 3 DRIVE MECHANISM The Diskette drive motor rotates the spindle at 360 rpm through a belt drive system 50 or 60 Hz power is ac ...

Page 310: ...HEAD LOAD OPTiONAl STEP INDEX DIRECTION SIDE SELECT OPTIONAl DRIVE SELECT READ LOGIC WRITE lOGIC CONTROL LOGIC SIDE SELECTI POWER ON RESET HEAD 1 HEAD 0 il II II tJ r II 11 II II v TRACK 00 DETECTOR I V Jr I I TRACK 00 LED SECTOR 851 ALTERNATE I O 3 LINES TWO SIDED OPTIONAl DISK CHANGE INDEX DETECTO_R INDEX LED FIGURE 1 SA8S0 8S1 FUNCTIONAL DIAGRAM ...

Page 311: ...terchangeability The diskette is heid in a plane perpendicular to the read write heads by a platen located on the base casting This precise registration assures perfect compliance with the read write heads The fiexure mounted head is loaded against its rigidly mounted counterpart via the head load solenoid The read write heads are in direct contact with the diskette The head surface has been desig...

Page 312: ...tput lines light the Activity LED on the front of the drive and lock the door Optional modes ot drive selection are discussed in Section 7 3 3 TRACK ACCESSING Seeking the read write head from one track to another is accomplished by a Activating Drive Select line b Selecting desired direction utilizing Direction Select line c Write Gate being inactive d Pulsing the Step line Multiple track accessin...

Page 313: ...DC POWER DRIVE SELECT DIRECTION SELECT STEP 55 SS OUT IN rs I lJ l S MIN j 1 ms MIN FIGURE 2 TRACK ACCESS TIMING 8 ...

Page 314: ...lect changes state before a read or write operation can be initiated Figure 3 shows the use of Side Select prior to a read operation Two jumper selectable Side Select options are also available Either of these can be implemented to make use of existing controller and cable harness design These options are described fully in Section 7 ss DC POWER DRIVE SELECT I SC I SS STEP 1 gOms 100 5 MIN SIDE SE...

Page 315: ...PARISONS I A B SEP DATA 851 __ 1__ 0 ONLY READ DATA 1 I A 4 00 S NOM 2 00p 5 NOM 2 00p s NOM J I 200 50n5 SEP CLOCK 851 IU _ lU ONLY U l 1 200 50n5 u A LEADING EDGE OF BIT MAY BE 400n5 FROM ITS NOMINAL POSITION B LEADING EDGE OF BIT MAY BE 200n5 FROM ITS NOMINAL POSITION FIGURE 5 READ SIGNAL TIMING FM ENCODING 10 ...

Page 316: ...he current bit cell if either the preceding bit cellar the current bit cell contains a data bit See Figure 4 b M2FM The clock bit is omitted from the current bit cell if the preceding bit cell contained any bit clock or data or if the current bit cell contains a data bit See Figure 4 In all three of these encoding schemes clock bits are written at the start of their respective bit cells and data b...

Page 317: ... are required in order to guarantee that the read write head position has stabilized prior to writing Write data encoding can be FM MFM or M2FM If either double frequency encoding scheme is used MFM or M2FM the write data should be precompensated to counter the effects of bit shift The amount and direc tion of compensation required for any given bit in the data stream depends on the pattern it for...

Page 318: ...Ot I r 50MSMIN U I 1 r 18 MS MIN WRITE GATE _ j 1 400 5 MAX WRITE DATA U U 2 SECONDS IF AC AND DC POWER ARE APPLIED AT SAME TIME FIGURE 6 WRITE INITIATE TIMING WRITE DATA IFM 150n5MIN 1100ns MAX FIGURE 7 WRITE DATA TIMING FM ENCODING 13 ...

Page 319: ...NOTE 1 1 4 S MAX I I I Tul j r 8mSMIN SO SMIN IFNOTE 1 4 n P H LrU 90 ms MAX J 2 SECONDS IF AC AND DC POWER ARE APPLIED AT SAME TIME WHEN CHANGING DIRECTION ON THE HEAD A 15 MS DELAY MUST BE INTRODUCED NOTE 1 50 ms minimum delay must be introduced after Drive Select to allow for proper head load settling If stepper power is to be applied independent 01 Head Load then a 15 ms minimum delay must be ...

Page 320: ...er iSIPl Sf lf T OPTI READ DATA WRIH GATE STI I SfP DAlA 18 0 Qr l jlliH DATA WR IL pm He 1 __ln 1C1IV I S l l f C 1 IO I SC LCIC C Co r TC o l 26 DCGND 24 VDC y 24 v RETURN J4 FRAME GND jt _1 AC U T 1 fRAME ROUND AC GNO 17 AC INPUT gTWISTi O PAIR L J These lines are alternate inputloutput lines and they are enabied by Jumper plugs ReJerence Section lIar uses of these Imes Not shown are pins 6 and...

Page 321: ...vide signals to the host output via Interface connector P1 J1 4 1 1 INPUT LINES There are thirteen 13 signal input lines ten 10 are standard and three 3 are user installable options reference section 7 The input signals are of two types those intended to be multiplexed in a multiple drive system and those which will pertorm the multiplexing The input signals to be multiplexed are 1 Direction Selec...

Page 322: ...e on the Inteface 2 External termination may be used provided the terminator is beyond the last drive Each of the five lines should be terminated by using a 150 ohm V watt resistor pUlled up to 5VDC The same removable resistor pack is also provided for terminating the optional input lines 4 1 1 2 DRIVE SELECT 1 4 Drive Select when activated to a logical zero level activates the multiplexed I O lin...

Page 323: ...OTE A 15ms delay must be Introduced when changing direction i e the last step in pulse to first step out pulse or vice versa 4 1 1 5 STEP This interface line is a control Signal which causes the read write heads to move with the direction of motion as defined by the Direction Select line The access motion is initiated on each logical zero to logical one transition or the trailing edge of the signa...

Page 324: ...kette 166 67 ms to indicate the beginning of the track Normally this signal is a logical one and makes the transition to the logical zero level for a period of 1 8 ms OA ms on SA851 once each revolution The timing for this signal IS shown In Figure 11 To correctly detect Index at the control unit Index should be false at Drive Select time that is the controller should see the transition from false...

Page 325: ...ignai is a logical one level and becomes a logical zero level for the active state Reference Figure 5 for the timing 4 1 2 7 SEP CLOCK SA851 only This interface line furnishes the clOck bits as separated from the raw data by use of the internal data separator Normally this signal is a logical one level and becomes a logical zero level for the active state Reference Figure 5 for the timing 4 1 2 8 ...

Page 326: ...Frame Gnd Frame Gnd 3 85 127VRtn 170 253 V Rtn 85 127 V Rtn 170 253 V Rtn MAX 0 35 Amps 0 25 Amps 0 35 Amps 0 25 Amps CURRENT FREQ 0 5 Hz 0 5 Hz TOLERANCE TABLE 1 4 2 2 DC POWER DC power to the drive IS via connector P5 J5 located on the non component side ot the PCB near the P4 con nector The two DC voltages and their specltications along with their P5 J5 pin deSignators are outlined In Table 2 P...

Page 327: ...or are shown in Figure 13 The pins are numbered 1 through 50 with the even numbered pins on the component side of the PCB and the odd numbered pins on the non component side Pin 2 is located on the end of the PCB connec tor closest to the AC motor capacitor and is labeled 2 A key slot is provided between pins 4 and 6 for op tional connector keying The recommended connectors for P1 are tabulated be...

Page 328: ...from non component side 5 3 J4IP4 CONNECTOR The AC power connector J4 is mounted on the AC motor capacitor bracket and is located just below the capacitor J4 connector is a 3 pin connector AMP PIN 1 480701 0 with pins PIN 350687 1 2 EA and 350654 1 1 EA The recommended mating connector P4 IS AMP PIN 1 480700 0 utilizing pins 350550 1 Figure 15 illustrates J4 connector as seen from the rear of the ...

Page 329: ...ECOMMENDATIONS The SA850 851 is capable of being mounted in one of the following positions refer to Figure 17 1 Vertical Door opening to the left or right 2 Horizontal Door opening up pCB down 3 Upright To mount the drive in this position remove the spring hook attached to the eject mechanism and attach the eject spring to the post the spring hook was attached to DOOR OK B NOT RECOMMENDED FIGURE 1...

Page 330: ...All dimensions are in inches m ill m ill 18 32 7X m Decorative Cover Dimensions Cover Size Dim A Dim B Dime 4 5 8 x 10 1 2 10 SO 240 462 5 114 x 10 10 00 240 5 25 5 114 x 11 11 00 740 525 Tolerance O3 030 Q3 l IJ r40 02 I o 02T40 02 1 MOUNTING 2Xl 2X ASLIDE D I ill I or I iUNCTIONAL FACEPLATE 0 w 0 I w O l 0 0 0 w Or U L _ I J 11 1 MOUNTING 140 100 798 2X i5 c zl m en 0 Q CD 0 Cii m j m en i 0 JJ ...

Page 331: ...hickness 3 Functional front plate height 7 Functional front plate thickness 4 Cosmetic front cover width 8 Cosmetic front cover color comes only in tan t o t g 54 f 1REFI 1 I o D l x Q 0 N I G I 4 62 03 249 02 I I i I I X x 0 t I u S 0 Xl N X X N N 0 Z t 0 Xl I L __ I T 11 450 02 I 1 462 02 FIGURE 19 SA850 851R DIMENSIONS 26 ...

Page 332: ...ith one of the following decorative face plates SIZE COLOR 4518 x 101 2 Tan 4518 x 101 2 White 51 4 x 10 Tan 51 4 x 10 White 5 1 4 x 11 Tan 5 1 4 x 11 White R Series 4 5 8 x 811 16 Tan If another color is required to match the system s color scheme the face plate may be painted The follow ing information should be utilized to avoid potential problems in the painting process 1 The front cover is ma...

Page 333: ...lug Shugart PIN 15648 or AMP PIN 53013 2 This section will discuss a few examples of modifications and how to install them The examples are 1 Select drive without loading head or enabling stepper 2 Select drive and enable stepper without loading head 3 Load head without selecting drive or enabling stepper 4 Radial Ready 5 Radial Index Sector 6 In Use Activity LED optional input 7 Write Protect opt...

Page 334: ...de Select Input Pluaaed S3 Side Select Uption Using Drive elect X TS FS Data Separation Option Select TS FS Plugged IW Write Current Switch Pluaged RS Ready Standard Plugged RM Readv Modified X HLL Head Load Latch X IT In Use Terminator Plugged HI Head Load Or In Use to the In Use Circuit X F Remove for MFM encodtng Install for M FM X AF Install for FM or MFM encoding Pluaaed NF Install for M FM e...

Page 335: ...c C es o 00 8 H mR 0 W 8g Ill C C l 0 I CTID mLr C IJ 00 cI J aD ceo 0 1 I B G1D c CIl l U 0 I c I e 0 p no l rna cb f f nIIJ u D Q o 6 L f_ o u D D 00 FIGURE 21 MLC 10 COMPONENT LOCATIONS PIN 25188 30 ...

Page 336: ...t t x G m i i t J 4 I m illC r O 41 mo mo illD 000000 CB I _ 00 iC 3 E 0 illc i 0 0 It I S ID O on 143 o ffi is o 118 m Eb r I I I I I I L I 00 I I 18 DS Jl Jl B DSJ J8 0 0 I FIGURE 22 MLC 11 PCB COMPONENT LOCATIONS PIN 25200 31 ...

Page 337: ...n on a standard drive the fOllowing traces should be deleted or added 1 Cut trace X 2 Jumper trace C 7 2 SELECT DRIVE AND ENABLE STEPPER WITHOUT LOADING HEADS This option is useful to the user who wishes to select a drive and perform a seek operation without the heads being loaded or with door open An example use ot this option is that at power on time an automatic recalibrate reverse seek to trac...

Page 338: ...OUT SELECTING DRIVE OR ENABLING STEPPER This option IS useful in disk to disk copy operations It aliows the user to keep the heads loaded on all drives thereby eliminating the 50 ms head load time The heads are kept loaded on each drive via an Alternate I O pin Each drive may have its own Head Load line Radial or Simplexed or they may share the same line Multiplexed When the drive is selected an 1...

Page 339: ... DRIVE SELECT 4 30 DRIVE SELECT 3 28 DRIVE SELECT 2 26 DRIVE SELECT 1 N j j j 0 0 0 0 STANDARD TRACE fj DELETED TRACE ADDED OR JUMPERED TRACE DD 4 4 t ALTERNATE 6 6 j 110 PINS at I 8 DRIVE u J SELECT 18 18 1 HEAD LOAD ft A I 5VDC 150 B ooo C x DOOR CLOSED I _ HEAD r L_ LOAD If the Head Load line is mUltiplexed termination pack 5E must be removed from each drive except the last one on the line FIGU...

Page 340: ...d be deleted or added 1 Cut trace RR 2 Cut trace R 3 Add a wire from pad R to one of the Alternate I O pins One of the drives on the interface may use pin 22 as its Ready line therefore steps 2 and 3 may be eliminated on this drive All the other drives on the interface must have their own Ready line therefore step 2 and 3 must be incorporated Figure 26 illustrates the circuitry 8 R 22 1 i i 1 READ...

Page 341: ...trace I to one of the Alternate 110 pins 5 Add a wire from trace S to one of the Alternate 110 pins One of the drives on the interface may use pin 20 Index and pin 24 Sector as its Index and Sector lines therefore steps 2 5 may be eliminated for this drive All other drives on the interface must have their own In dex and Sector lines therefore steps 2 5 must be incorporated Figure 27 illustrates th...

Page 342: ...ITO LED J2 li7 DOOR LOCK WRITE GATE FIGURE 28 IN USE ACTIVITY LED CIRCUIT 7 7 WRITE PROTECT OPTIONAL USE As shipped from the factory the optional Write Protect feature will internally inhibit writing when a Write Pro tected Diskette is installed With this option installed a Write Protected Diskette will not inhibit writing but it will be reported to the interface This option may be useful in ident...

Page 343: ...if while deselected the drive has gone from a Ready to a Not Ready Door Open condition This line is reset on the true to false transition of Drive Select if the drive has gone Ready Timing of this line is illustrated in Figure 30 The circuitry is Illustrated In Figure 31 DRV SEL READY DISK CHG FIGURE 30 DISK CHANGE TIMING 5V D 0 C 00 READY DRV SEL FIGURE 31 DISK CHANGE CIRCUIT 38 DC 12 12 DISK CHG...

Page 344: ...controls the direction of head motion during stepping operations and controis side head selection during read write operations To implement this option simply move jumper S2 to location S1 Figure 32 illustrates the circuitry DRIVE SELECT SIDE 0 rCl jr 1 _ CT S2 SIDE SELECT S1 DIRECTION SELECT 4I X SIDE SELECT SIDE 1 CT FIGURE 32 SIDE SELECTION USING DIRECTION SELECT 39 ...

Page 345: ...rs installed at DS1 and 28 while the second drive has jumpers at DS3 and 48 With this jumper configuration installed the four Drive Select lines have the following side selection functions 1 Drive Select 1 selects side 0 of first drive 2 Drive Select 2 selects side 1 of first drive 3 Drive Select 3 selects side 0 of second drive 4 Drive Select 4 selects side 1 of second drive Figure 33 illustrates...

Page 346: ...e a latch will be set which holds the door lock circuit active To unlock the door Drive Select is again activated while In Use is inactive Figure 34 illustrates the circuitry for this option 5V TO IN USE LED DRIVER IN USE if DRIVE SELECT INT HI D DL o Q C FIGURE 34 DOOR LOCK LATCH CONTROL TO DOOR LOCK DRIVER 7 12 TWO SIDED OPTIONAL OUTPUT This signal indicates whether a Two Sided True Output or a ...

Page 347: ...ctivated to a logical zero level the read signal is passed through an active filter network for reading tracks 60 through 76 Performance will improve when reading a diskette that has been recorded without write precompensation To control the active read filter from the interface short trace IW to connect to the interface remove Jumpers AF and NF When the Interface is activated to a logical zero le...

Page 348: ...er to figure 36 If In Use is to be used jumper pin 0 to pin HI refer to figure 37 In both cases trace A on shunt 4F must be cut To load and latch the heads the user must activate either the Head Load or In Use lines and select the drive When the drive is deselected the heads will stay loaded and the door locked To unload the heads the Head Load or In Use line must be inactive when the drive is sel...

Page 349: ...A B HLL FIGURE 37 HEAD LOAD LATCH USING IN USE 44 ...

Page 350: ...ive spindle rotating When removed from the drive the diskette Is stored in an envelope To protect the diskette the same care and handling procedures specified for computer magnetic tape apply These precautionary procedures are as follows 1 Return the diskette to its storage envelope whenever it is removed from drive 2 Keep diskettes away from magnetic fields and from ferromagnetic materials which ...

Page 351: ...ng the rear of the slot The Diskette can then be write protected by removing the tab See Figure 39 8 3 WRITE PROTECT IBM DISKETTES IBM Diskettes are not manutactured with a write protect slot punched out as are the Shugart Diskettes To Write Protect one of these diskettes a slot must be punched out as specified in Figure 40 The operation of the write protect is that which is outlined in paragraph ...

Page 352: ...iper 2 Random electrical noise which usually lasts for a few microseconds 3 Small defects in the written data and or track not detected during the write operation which may cause a soft error during a read The following procedures are recommended to recover from the above mentioned soft errors 1 Reread the track ten 10 times or until such time as the data is recovered 2 If data is not recovered af...

Page 353: ...LATCH STOP SHIPPING DISK FIGURE 41 PACKAGE ASSEMBLY 48 ...

Page 354: ...MINIMUM LOAD MAXIMUM LOAD FIGURE 42 PALLET LOADING 49 ...

Page 355: ...E PLATES Size Color Part Numbers 4 5 8 X 10 1 2 Tan 50264 4 5 8 x 10 1 2 White 50263 5 1 4 x 10 Tan 50261 5 1 4 x 10 White 50260 5 1 4 x 11 Tan 50258 5 1 4 x 11 White 50257 Rack Mount 4 5 8 x 8 11 16 Tan 50675 Primary Voltage Part Numbers and Motor Motor Frequency ASM Pulley Belt 115 VAC 60 Hz 50747 50358 50356 115VAC 50 Hz 50747 50357 50355 230 VAC 60 Hz 50748 50358 50356 230 VAC 50 Hz 50748 5035...

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