ZWorld Exp-A/D12, User Manual

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XP8500
and
Exp-A/D12 PLCBus s 79
Place an address on the bus by writing (bytes) to BUSADR0, BUSADR1
and BUSADR2 in succession. Since 4-bit and 8-bit addressing modes
must coexist, the lower four bits of the first address byte (written to
BUSADR0) identify addressing categories, and distinguish 4-bit and 8-bit
modes from each other.
There are 16 address categories, as listed in Table A-3. An “x” indicates
that the address bit may be a “1” or a “0.”
Table A-3. First-Level PLCBus Address Coding
First Byte Mode Addresses Full Address Encoding
– – – – 0 0 0 0
– – – – 0 0 0 1
– – – – 0 0 1 0
– – – – 0 0 1 1
4 bits × 3 256
256
256
256
0000 xxxx xxxx
0001 xxxx xxxx
0010 xxxx xxxx
0011 xxxx xxxx
– – – x 0 1 0 0
– – – x 0 1 0 1
– – – x 0 1 1 0
– – – x 0 1 1 1
5 bits × 3 2,048
2,048
2,048
2,048
x0100 xxxxx xxxxx
x0101 xxxxx xxxxx
x0110 xxxxx xxxxx
x0111 xxxxx xxxxx
– – x x 1 0 0 0
– – x x 1 0 0 1
6 bits × 3 16,384
16,384
xx1000 xxxxxx xxxxxx
xx1001 xxxxxx xxxxxx
– – x x 1 0 1 0 6 bits × 1 4 xx1010
– – – – 1 0 1 1 4 bits × 1 1 1011 (expansion register)
x x x x 1 1 0 0 8 bits × 2 4,096 xxxx1100 xxxxxxxx
x x x x 1 1 0 1 8 bits × 3 1M xxxx1101 xxxxxxxx xxxxxxxx
x x x x 1 1 1 0 8 bits × 1 16 xxxx1110
x x x x 1 1 1 1 8 bits × 1 16 xxxx1111
This scheme uses less than the full addressing space. The mode notation
indicates how many bus address cycles must take place and how many bits
are placed on the bus during each cycle. For example, the 5 × 3 mode
means three bus cycles with five address bits each time to yield 15-bit
addresses, not 24-bit addresses, since the bus uses only the lower five bits
of the three address bytes.