ZLIM57 Integrated Open Loop Step Motor Manual Version 1.01
ZLIM57 Integrated Open Loop Step Motor Manual Version 1.01
11
Shenzhen ZhongLing Technology Co.,Ltd. TEL: +86-0755-29799302 FAX
：
+86-0755-2912 4283 WEB:
Shenzhen ZhongLing Technology Co.,Ltd. TEL: +86-0755-29799302 FAX
：
+86-0755-2912 4283 WEB:
12
Fig.2 Control signal interface wiring diagram
If input control signal single-ended, its control signal interface wiring diagram is shown
in Figure 3:
Fig.3 Input interface circuit
Note: The default input voltage of the control signal is 5V. For other voltages, current
limiting resistors must be added. For example: 12V, external 1K 1 / 2W resistor; 24V,
external 2K 1 / 2W resistor.
Control signal timing diagram
In order to avoid some wrong actions and deviations, PUL, DIR and ENA should meet
certain requirements, as shown below:
Fig.4 Control signal timing diagram
Note:
1) t1: ENA (enable signal) should be confirmed to be high at least 100ms ahead of DIR,
to ensure that the brake is open, and the motor enters running state, to avoid
abnormality.
2) t2: DIR is confirmed for its state to be high or low at least 5μs ahead of PUL falling
edge.
3) t3: The pulse width is at least not less than 2.5μs.
4) t4: The low level width is not less than 2.5μs.
3.3. Output Signal Wiring
Signal output wiring, such as alarm signal output ALM, photoelectric isolation OC
output, maximum withstand voltage 30VDC, maximum saturation current 50mA.
ALM-
ALM+
Fig.5 Output Signal Wiring
3.4. Status Indicator LED
