CONFIDENTIAL
Z3-DM816X-PCI2-RPS V2.00.00
___________________________________________________________________________________________
Z3 Technology, LLC
♦
100 N 8
th
ST, STE 250
♦
Lincoln, NE 68508-1369 USA
♦
+1.402.323.0702
30
motherboard.
Z3 Technology recommends that development with the DM816X-PC2I-RPS be done on an Asus P8H67-MPRO
motherboard. The BIOS on this system has been verified to perform correctly.
The systems with “bad BIOS” tend to work correctly when the add-in card is plugged into the 1-lane slot,
when present. This can be accomplished with a PCIe to PCIe adapter or when the 1-lane slot connector on
the motherboard is open at the edge to allow insertion of boards with more than 1 lane.
10.3 The DM816X-MOD-3X PCIe Hardware
The PCI Express bus is not really a “bus”. Instead, it is a point-to-point connection between a PCI master
and a slave. The PCI master can send commands to perform PCI transactions, and the slave carries them
out. The PCIe interface on the master side is called the “root complex”, and the interface on the slave
side is called the “endpoint.” A computer or any device with a slot is the root complex, while anything
the plugs into the slot is the endpoint.
The Z3-DM816X-MOD-3X module is capable of being a root complex or an endpoint. In order for the Z3
module to be used in a specific PCIe setting, the module must have the proper configuration. By default,
Z3 ships Z3-DM816X-MOD-2X modules configured as a root complex, and Z3-DM816X-MOD-3X modules
configured as an endpoint. The Z3-DM816X-PCI2-RPS kit contains a Z3-DM816X-MOD-3X module, and
therefore is by default configured as an endpoint.
The difference between the two from the hardware level is the PCIe clock generation. PCIe requires that
the root complex provide a 100 MHz clock to the endpoint. The DM816X processor uses this clock to drive
its internal PCIe interface. So when a module is configured as root complex, it will provide the 100 MHz
clock to the processor and to the PCIe bus. When the module is configured as an endpoint, the PCIe bus
clock is an input to be driven from the root complex, and it is required to drive the PCI Express interface
on the DM8168 chip.
Another point to keep in mind is that the same PCIe interface on the chip is used for both root complex
and endpoint configurations. The software needs to be set to operate in the right mode or the DM816X
system will not work as expected. In particular, if the board is set up for endpoint operation and the Linux
kernel is configured for root complex, the kernel will hang waiting for the PCIe clock during initialization
and the module will not boot.
