17
HE4K-DCK-1x & FV4K-DCK-1x
HARDWARE SPECIFICATION
CONFIDENTIAL
DOC-USR-0100-09
____________________________________________________________________________________
Z3 Technology, LLC
♦
100 N. 8th St. STE 250
♦
Lincoln, NE 68508-1369 USA
♦
+1.402.323.0702
Pin Signal
Pin Signal
1
Hot Plug Detect
11 Data0-
2
Utility
12 Clock+
3
Data2+
13 Gnd
4
Gnd
14 Clock-
5
Data2-
15 CEC
6
Data1+
16 GND
7
Gnd
17 DDC_CLK
8
Data1-
18 DDC_DAT
9
Data0+
19 +5V
10
Gnd
Table 4 IFE PCB J2 Pin Out
7.1.3
J3
–
FPGA JTAG
J3 is a debug connector providing access to the JTAG port of the FPGA. Its pin assignment is shown in
that table below.
This connector is usually not placed on the PCB.
When a header is placed, it will be a standard 1.27mm male header, Sullins GRPB061VWVN-RC or
similar.
Pin Signal
Pin Signal
1
TMS
4
TCK
2
TDI
5
GND
3
TDO
6
+3.3V
Table 5 IFE PCB J3 Pin Out
7.1.4
J4
–
Connection with Main Encoder PCB
Connector J4, located on the bottom side of the PCB, provides all the connectivity between the IFE
board and the encoder board. Even numbered pins 2 to 22 provide access to the FPG for
configuration and control.
This is a 90-pin, 0.4 mm pitch board-to-board connector. The Front End PCB uses a Hirose DF40C-
90DP-0.4V(51) connector or equivalent.
This connector mates with J7 on the Main Encoder PCB.
Pin Signal
Pin Signal
1
GND
2
STATUS_SELECT
3
MIPI0_D1M
4
STATUS_OUT
5
MIPI0_D1P
6
I2C_SDA
7
GND
8
I2C_SCL
