A
1
2
3
4
5
6
7
8
9
10
B
C
D
E
F
G
H
I
J
K
L
M
N
YSP-1000
SCHEMATIC DIAGRAM (OPERATION)
68
★
All voltages are measured with a 10M
Ω
/V DC electronic volt meter.
★
Components having special characteristics are marked
s
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
0
5.1
6.8
0
-22.5
-22.4
3.3
-22.5
-22.4
3.3
-22.5
-22.4
-22.5
-17.8
-16.2
-22.5
-24.1
-24.1
-17.7
-17.8
-19.3
-19.3
-19.3
-17.8
-22.5
-22.5
-17.8
-19.3
-21.0
-19.3
-21.0
-17.8
-19.3
-20.9
-19.3
-22.5
-16.2
-19.3
3.3
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-24.1
-17.8
3.3
1.5
0
3.2
3.2
3.2
3.2
3.3
0
0
5.1
5.1
5.1
1.4
5
5.1
6
12.0
4.8
6.8
5.1
0
3
2
4.9
4.6
4.6
12.0
-24.1
-17.5
-17.8
-17.8
3.3
-22.5
-22.5
3.3
-17.8
-17.9
3.3
-19.2
-19.3
3.3
-24.1
-24.7
3.3
0
4.9
0.3
0
0
3.3
0
4.6
-17.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-17.8
-19.3
-19.3
-19.3
-17.8
-17.7
-24.1
-24.1
-22.5
-16.2
-17.8
-22.5
-22.5
-22.5
-17.8
-19.3
-21.0
-19.3
-21.0
-17.8
-19.3
-20.9
-19.3
-22.5
-16.2
-19.3
-22.5
-24.1
-22.5
-16.2
-19.2
-17.8
-17.8
-17.8
-17.8
-17.5
52
Display
controller
Segment
digit
select/
output
circuit
Serial
receive
circuit
Digit
output
circuit
Clock
generator
G12
51
G13
50
G14
49
48
47
P38
46
P37
45
P36
XOUT
6
VDD
8
Vcc2
18
Vss
5
Vp
64
XIN
7
3
4
/RESET
1
P35
44
9
P1
P9
17
19
P10
Segment
output
circuit
Display code
RAM
(8-bit x 60)
CGROM
(35 bit x 166)
CGROM
(35 bit x 16)
code
select
Code
write
Code/
command
control
circuit
G1
63
53
G11
IC1
: M66003-0101FP
FL Display Driver
2
data
timing
clock
dot data
write
scan pulse
/CEFL
CKFL
DTFL
IC801
: NJM2068MD-TE2
Dual OP-Amp
–
+
OUT
1
–IN
1
–V
CC
+V
CC
OUT
2
1
2
3
4
5
+IN
1
–IN
2
+IN
2
–
+
6
7
8
OPERATION (1)
FL DISPLAY
FRONT SW
IR-IN
OPERATION (4)
OPERATION (3)
OPERATION (2)
OPTIMAIZER MIC
Page 63
to DSP_CB7
L6
Page 67
to INPUT (3)_W401
E8
Page 63
to DSP_CB6
L5
Summary of Contents for YSP 1000 - Digital Sound Projector Five CH...
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