102
TF5/TF3/TF1
PIN
NO.
NAME
I/O
FUNCTION
PIN
NO.
NAME
I/O
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PWRHOLD
VMMC
VCC3
VAUX33
VDIG2
VCC6
VDIG1
SDA/SDI
SCL/SCK
SDASR/EN2
SCLSR/EN1
VDDIO
VCCIO
SWIO
GNDIO
VFBIO
REFGND
VREF
BOOT1
OSC32KIN
OSC32KOUT
VDAC
VCC5
I
O
I
O
O
I
O
I/O
I/O
I/O
I/O
I
I
O
I/O
I
I/O
O
I
I
I
O
I
Switch-on/-off control signal
LDO regulator output
VMMC VAUX33 power input
LDO regulator output, VDD3 internal
regulated supply
LDO regulator output
VDIG1, VDIG2 power input
LDO regulator output
I2C bidirectional data signal/serial peripheral
interface data input (multiplexed)
I2C bidirectional clock signal/serial peripheral
interface Clock Input (multiplexed)
I2C SmartReflex bidirectional data signal/
enable of supplies (multiplexed)
I2C SmartReflex bidirectional clock signal/
enable of supplies (multiplexed)
Digital I/Os supply
VIO DC-DC power input
VIO DC-DC switched output
VIO DC-DC power ground
VIO feedback voltage
Reference ground
Bandgap voltage
Power-up sequence selection
32-kHz crystal oscillator
32-kHz crystal oscillator
LDO regulator output
VDAC, VPLL power input
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VPLL
TESTV
BOOT0
VBACKUP
VCC7
VRTC
VFB3
SW3
VFB1
PWRON
GND1
SW1
VCC1
SLEEP
CLK32KOUT
GPIO/CKSYNC
NRESPWRON
VCC2
SW2
GND2
VFB2
INT1
VAUX1
VCC4
VAUX2
GNDP
O
O
I
I
I
O
I
O
I
I
I/O
O
I
I
O
I/O
O
I
O
I/O
I
O
O
I
O
-
LDO regulator output
Analog test output (DFT)
Power-up sequence selection
Backup battery input (short to VCC5 if not used)
VRTC power input, VDD3 internal and analog
references supply
LDO regulator output
VDD3 feedback voltage
VDD3 DC-DC switched output
VDD1 feedback voltage
External switch-on control (ON button)
VDD1 DC-DC power ground
VDD1 DC-DC switched output
VDD1 DC-DC power input
Active-sleep state transition control signal
32-kHz clock output
Configurable general-purpose I/O or DC-DCs
synchronization clock input signal
Power off reset
VDD2 DC-DC power input
VDD2 DC-DC switched output
VDD2 DC-DC power ground
VDD2 DC-DC feedback voltage
Interrupt flag
LDO regulator output
VAUX1, VAUX2 power input
LDO regulator output
Ground
TPS65910AA1RS
(YF900A00)
POWER MANAGEMENT IC
MAIN (MAINCOM): IC903
PIN
NO.
NAME
I/O
FUNCTION
PIN
NO.
NAME
I/O
FUNCTION
1
2
3
4
5
6
7
8
9
10
VDD2A
LED2/
nINTSEL
LED1/
REGOFF
XTAL2
XTAL1/
CLKIN
VDDCR
RXD1/
MODE1
RXD0/
MODE0
VDDIO
RXER/
PHYAD0
-
I/O
I/O
O
I
-
I/O
I/O
-
I/O
+3.3V Analog Port Power to Channel 2 and
the internal regulator.
Link Speed LED Indication./This configuration
strap selects the mode of the nINT/REFCLKO pin.
Link activity LED Indication./This configuration
strap is used to disable the internal 1.2V regulator.
External crystal output.
External crystal input./Single-ended clock
oscillator input.
Supplied by the on-chip regulator unless
configured for regulator off mode via the
REGOFF configuration strap.
Bit 1 of the 2 data bits that are sent by the
transceiver on the receive path./Combined
with MODE0 and MODE2, this configuration
strap sets the default PHY mode.
Bit 0 of the 2 data bits that are sent by the
transceiver on the receive path./Combined
with MODE1 and MODE2, this configuration
strap sets the default PHY mode.
+1.6V to +3.6V variable I/O power.
This signal is asserted to indicate that
an error was detected somewhere in the
frame presently being transferred from the
transceiver./This configuration strap sets the
transceiver’s SMI address.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CRS_DV/
MODE2
MDIO
MDC
nINT/
REFCLKO
nRST
TXEN
TXD0
TXD1
VDD1A
TXN
TXP
RXN
RXP
RBIAS
VSS
I/O
I/O
I
O
I
I
I
I
-
I/O
I/O
I/O
I/O
I
-
This signal is asserted to indicate the receive
medium is non-idle./Combined with MODE0
and MODE1, this configuration strap sets the
default PHY mode.
Serial Management Interface data input/
output.
Serial Management Interface clock.
Active low interrupt output./This optional
50MHz clock output is derived from the
25MHz crystal oscillator.
System reset.
Indicates that valid transmission data is
present on TXD[1:0].
The MAC transmits data to the transceiver
using this signal.
The MAC transmits data to the transceiver
using this signal.
+3.3V Analog Port Power to Channel 1.
Transmit/Receive Negative Channel 1.
Transmit/Receive Positive Channel 1.
Transmit/Receive Negative Channel 2.
Transmit/Receive Positive Channel 2.
This pin requires connection of a 12.1k ohm
(1%) resistor to ground.
Common ground.
LAN8720A-CP-TR
(YF905A00)
ETHERNET TRANSCEIVER
(PHY)
MAIN (MAINCOM): IC915
Summary of Contents for TF5
Page 10: ...10 TF5 TF3 TF1 866 716 225 599 225 599 TF5 TF3 Unit mm Unit mm DIMENSIONS...
Page 11: ...11 TF5 TF3 TF1 225 510 599 TF1 Unit mm...
Page 110: ...B B MAIN MAINCOM Circuit Board 2NA0 ZJ06330 3 110 TF5 TF3 TF1...
Page 111: ...B B Scale 90 100 Pattern side 2NA0 ZJ06330 3 111 TF5 TF3 TF1...
Page 113: ...WR 1 WR 1 DA2 Circuit Board Scale 90 100 Component side 2NA ZJ06430 2 113 TF5 TF3 TF1...
Page 116: ...WR 1 WR 1 7 WR 32 5 6 C C PS Circuit Board 2NA ZJ06320 2 116 TF5 TF3 TF1...
Page 119: ...Component side D D Component side 2NA ZJ06380 4 119 TF5 TF3 TF1...
Page 166: ...TF5 TF3 TF1 166 q w e r PLAY q PASS FAIL w CLOSE USER DEFINED KEYS B...
Page 202: ...TF5 TF3 TF1 202 7 SYSTEM SETUP ABOUT 8 HOME Initialize All Memory CANCEL OK OK EXIT...
