Yamaha RX-V757, Service Manual

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RX-V757/DSP-AX757/DSP-AX757SE
RX-V657/HTR-5860
RX-V757/DSP-AX757/DSP-AX757SE
RX-V657/HTR-5860
IC5 : D60YA003BPYP225 (DSP P.C.B.)
Decoder
Pin Multiple
xing
EMIF32
L1P Cache
Direct Mapped
4K Bytes Total
Digital Signal Processors
L1D Cache
2-Way Set
Associative
4K Bytes Total
Clock Generator,
Oscillator and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
Power-Down
Logic
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path B Data Path A
B Register File
Control
Registers
C67x
TM
CPU
Control
Logic
In-Circuit
Emulation
Interrupt
Control
Test
A Register File
.L1t
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
Timer 0
.S1t .M1t .D1 .D2 .M2t .S2t .L2t
GP1
GP0
HPI16
Enhanced
DMA
Controller
(16 channel)
L2 Cache/
Memory
4 Banks
64K Bytes
Total
(4-Way)
L2
Memory
DA610:
192K Bytes
DA601:
64K Bytes
R2 ROM
512K
Bytes
Total
No. Name [Default] I/O Function
1 GP0[4] / (EXT_INT4) IOZ General purpose I/O0 port 4 / Interrupt input (polarity selectable individually by using register)
2 GP0[6] / (EXT_INT6) IOZ General purpose I/O0 port 6 / Interrupt input (polarity selectable individually by using register)
3 CVDD S 1.2V power supply
4 VSS GND Ground
5 DVDD S 3.3V power supply
6 GP0[5] / (EXT_INT5) IOZ General purpose I/O0 port 5 / Interrupt input (polarity selectable individually by using register) (Unconnected)
7 GP0[7] / (EXT_INT7) IOZ General purpose I/O0 port 7 / Interrupt input (polarity selectable individually by using register) (Unconnected)
8 CLKS1 I McBSP1 external clock source
9 DVDD S 3.3V power supply
10 VSS GND Ground
11 CVDD S 1.2V power supply
12 TINP1 / AHCLKX0 I / IOZ Timer 1 Input / McASP0 Transmission MCLK
13 AXR1[11] IOZ McASP1 Transmission/reception data 11
14 CVDD S 1.2V power supply
15 VSS GND Ground
16 CLKX0 / ACLKX0 IOZ McBSP0 Transmission clock / McASP0 Transmission BCLK
17 AXR1[12] IOZ McASP1 Transmission/reception data 12
18 AXR1[13] IOZ McASP1 Transmission/reception data 13
19 ACLKR0 IOZ McASP0 Reception BCLK
20 DX0 O/Z McBSP0 Transmission data
21 FSX0 IOZ McBSP0 Transmission Frame Sync
22 CVDD S 1.2V power supply
23 VSS GND Ground
24 AFSR0 IOZ McASP0 Reception LRCLK
25 DVDD S 3.3V power supply
26 VSS GND Ground
27 DR0 I McBSP0 Reception data
28 AHCLKR0 IOZ McASP0 Reception MCLK
29 CVDD S 1.2V power supply
30 VSS GND Ground
31 FSX1 IOZ McBSP1 Transmission Frame Sync (Input in SPI slave state) (Unconnected)
32 AXR1[10] IOZ McASP1 Transmission/reception data 10
33 CLKX1 / AMUTE0 IOZ McBSP1 Transmission clock (Input in SPI slave state) / McASP0 MUTE output (Unconnected)
34 VSS GND Ground
35 CVDD S 1.2V power supply
36 AXR1[9] IOZ McASP1 Transmission/reception data 9
37 DR1 / SDA1 I / IOZ McBSP1 Reception data / I2C1 data (Unconnected)
38 AXR1[8] IOZ McASP1 Transmission/reception data 8
39 VSS GND Ground
40 CVDD S 1.2V power supply