Pin No.
Port Name
Function Name
Condition When Used
Detail of Function
I/O
Logic
M25
nRESET
VNP2_N_RST
I
L act
System reset terminal
T25
XI_S
–
I
Clock
System clock crystal oscillation terminal
T24
XO_S
–
O
Clock
System clock crystal oscillation terminal
AE24
XI_A
–
I
Clock
A
u
dio clock crystal oscillation terminal
AD24
XO_A
–
O
Clock
T22
TEST0
TEST0
I
H act
System reset terminal
R23
TEST1
–
I
H act
T23
TEST2
–
I
H act
L23
nSCS3
N_SCS3
O
BUS
Chip select 3
L24
nSCS2
N_SCS2
O
BUS
Chip select 2
K23
nSCS1
N_SCS1
O
BUS
Chip select 1
FLASH_N_CS
L24
nSCS0
N_SCS0
O
BUS
Chip select 0
J23
nSLBE
N_SLBE
O
BUS
Lower byte enable
J24
nSUBE
N_SUBE
O
BUS
Upper byte enable
K25
nSWR
N_SWE
O
BUS
Write enable
J25
nSRD
N_SRD
O
BUS
Read enable
**
SA[22:0]
SRA[22:0]
O
BUS
External I/O address b
u
s
**
SD[15:0]
SRD[15:0]
B
BUS
External I/O data b
u
s
B1
SCLK0
SDRAM_CLK0
O
Clock
SDRAM clock enable
C1
SCKE0
SDRAM_CKE0
O
H act
SDRAM clock enable
D1
SCLK1
SDRAM_CLK1
O
Clock
SDRAM clock enable
E1
SCKE1
SDRAM_CKE1
O
H act
SDRAM clock enable
F1
nCS1
–
O
BUS
SDRAM chip select 1
C2
nCS0
SDRAM_N_CS0
O
BUS
SDRAM chip select 0
E3
nWE
SDRAM_N_WE
O
BUS
SDRAM write enable
F2
nRAS
SDRAM_N_RAS
O
BUS
SDRAM row address strobe
E2
nCAS
SDRAM_N_CAS
O
BUS
SDRAM col
u
mn address strobe
A9
DQM3
SDRAM_DQM3
O
BUS
SDRAM data inp
u
t/O
u
tp
u
t mask 3
B9
DQM2
SDRAM_DQM2
O
BUS
SDRAM data inp
u
t/O
u
tp
u
t mask 2
C9
DQM1
SDRAM_DQM1
O
BUS
SDRAM data inp
u
t/O
u
tp
u
t mask 1
C10
DQM0
SDRAM_DQM0
O
BUS
SDRAM data inp
u
t/O
u
tp
u
t mask 0
**
A[12:0]
SDRAM_A[11:0]
O
BUS
SDRAM address b
u
s
J2
A13
SDRAM_BA0
O
BUS
SDRAM bank select BA0
J1
A14
SDRAM_BA1
O
BUS
SDRAM bank select BA1
**
D[31:0]
SDRAM_DQ[31:0]
B
BUS
SDRAM data b
u
s
45
NP-S20
0
0
NP-S2000