Pin No.
Port Name
Function Name
Condition When Used
Detail of Function
I/O
Logic
M24
nINT1
–
I
Interr
u
pt
Empty
M23
nINT2
PHY_N_INT
I
Interr
u
pt
Interr
u
pt from PHY
AE7
TXD0
DBG_TXD
O
UART TX
Serial for deb
u
gging
AE8
RXD0
DBG_RXD
I
UART RX
Serial for deb
u
gging
AD7
AGPIO[4]
DBG_LED0
O
Data
LED for deb
u
gging
AD8
AGPIO[1]
DBG_LED1
O
Data
LED for deb
u
gging
AC8
AGPIO[2]
NCPU_N_INT
O
Data
Interr
u
pt to main microprocessor
AE5
TXD1
NCPU_MISO
O
UART TX
Microprocessor comm
u
nication Main
→
S
u
b
AE6
RXD1
NCPU_MOSI
I
UART RX
Microprocessor comm
u
nication S
u
b
→
Main
AD5
AGPIO[10]
–
–
–
Empty
AD6
AGPIO[7]
–
–
–
Empty
AC6
AGPIO[8]
PHY01_N_RST
O
Data
PHY reset
AD4
AGPIO[13]
O
Data
Not
u
sed
AC5
AGPIO[11]
–
O
Data
Empty
AE4
ABPIO[12]
O
–
L: TAS1020B / H: Main microprocessor
AC7
AGPIO[5]
PLL_ON
O
–
Clock m
u
ltiplier PLL on/off
H: PLL / L: Thro
u
gh
AE2
AGPIO[18]
TEST_MAC
I
–
J
u
dgment of MAC address rewrite mode for servicing
L: MAC_Add rewrite men
u
in self-diagnostic f
u
nction
H: No s
u
ch men
u
in self-diagnostic f
u
nction
AE3
AGPIO[15]
I
–
H: TAS1020B enable / L: Disenable
AD2
AGPIO[19]
IP_N_RST
O
–
Apple certification chip reset
AD3
AGPIO[16]
DIX_N_RST
–
–
DIX9210 reset
AD1
AGPIO[20]
PHY0_N_100M
I
Data
H: Ether 10Mbps / L: Ether 100Mbps
AC4
PARITY/AGPIO[14]
PHY0_N_FDX
I
Data
H: Ether half d
u
plex / L: Ether f
u
ll d
u
plex
AC3
SIMRST/AGPIO[17]
PHY0_PD
O
Data
H: Ether low power / L: Ether normal power
AA1
I2C_SDA
EEP_DIT_SDA
B
Data
I2C EEPROM SDA/DIX9210 SDA
Y1
I2C_SCL
EEP_DIT_SCL
O
Clock
I2C EEPROM SCL/DIX9210 SCL
Y3
SPI_SCK
VNP2_FL_CLK
O
Clock
IF clock o
u
tp
u
t (VFD1/VFD2
↔
Main microprocessor)
For FL microprocessor control
W3
SPI_CS0
VNP2_FL_MISO
(Reserve)
I
Data
IF data inp
u
t (Reserve)
(VFD1/VFD2
↔
Main microprocessor)
For FL microprocessor control
V1
BGPIO[7]
No
u
sed
O
V2
BGPIO[8]
DAC_CSL
O
DAC (Lch) chip select
For PCM1792A control
V3
BGPIO[9]
AUD_CLK_SEL
O
No
u
sed (H: 22.5792MHz / L: 24.576MHz)
W1
BGPIO[4]
DAC_SDO
O
DAC data o
u
t
For PCM1792A control
46
NP-S20
0
0
NP-S2000
