Yamaha i88x Service Manual Download Page 19

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i88X

PIN

NO.

I/O

FUNCTION

NAME

PIN

NO.

I/O

FUNCTION

NAME

1
2
3
4
5
6
7
8
9

10
11

12
13
14
15
16
17

18
19

22
23

24
25

26
27
28
29

34
35

38
39
40

41
42
43
44
45
46
47

49
50
51
52

53
54

55
56

58
59
60
61
62
63
64
65
66
67
68
69

70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87

88
89
90

91
92

95
96

98
99

100

NC
NC

VCC

I/O209/TDI

I/O210

I/O211
I/O212
I/O213

PORT_EN

I/O214
I/O215
I/O216

I/O401/TMS

I/O402
I/O403

VCC

I/O404

I/O405

I/O406

I/O407

I/O408

GND

NC
NC

I/O409

I/O410

I/O411

I/O412

I/O413

VCC

I/O414

I/O415

I/O416

GND

VCC

I/O316

I/O315
I/O314

GND

I/O313
I/O312
I/O311
I/O310

I/O309

NC
NC

VCC

I/O308

I/O307

I/O306

I/O305

I/O304

GND

I/O303
I/O302

I/O301/TCK

I/O116
I/O115
I/O114

VCC

I/O113
I/O112
I/O111

I/O110

I/O109/TD0

GND

I/O108
I/O107

NC
NC

I/O106
I/O105
I/O104

VCC

I/O103
I/O102
I/O101

GND

IN3/CLK3

IN2/CLK2
IN1/CLK1
IN0/CLK0

VCC

I/O201

I/O202

I/O203

GND

I/O204

I/O205

I/O206
I/O207

I/O208

-
-
I
I
-
I
-
I
I
I
I

I
I
I
I
I

-
I

I
-
-

I
I

I
I
I
I

-
-
I

I
I
I
I
I
I
I
I
I
I
I

-
I
-

I/O
I/O

-
-

I/O
I/O
I/O

I
I

I
I
I

(Unconnected)
(Unconnected)
Power supply (3.3V)
Terminal for loading data
(Unconnected)
Terminal for reading 8th bit setting of DIP switch
(Unconnected)
Terminal for reading 7th bit setting of DIP switch
Terminal for reading 6th bit setting of DIP switch
Terminal for reading 5th bit setting of DIP switch
Terminal for selecting functions of pins No.4, 15, 62, 73
Connecting this terminal to GND changes the function of these
pins into data loading only
Terminal for reading 4th bit setting of DIP switch
Terminal for reading 3rd bit setting of DIP switch
Terminal for reading 2nd bit setting of DIP switch
Terminal for loading data
Terminal for reading 1st bit setting of DIP switch
Terminal for outputting clock as a result of ICLK (24.576MHz)
output from mLAN-NC1 divided by 8. This clock is connected to
pin No.42 (BCKI) of mLAN-NC1.
Power supply (+3.3V)
Output terminal of control signal to select clock for outputting
audio signal from mLAN-PH2. (H level: Clock usable for up to
Fs=96K is selected, L level: Clock unusable for Fs=96K is
selected) [Default on L level]
Terminal used so that inappropriate data immediately after
turning on the power is not output from MLN2 circuit board
against MIDI signal output from mLAN-NC1. (H level: Invalid data
is output, L level: Valid data is output)
This terminal changes to H level when MLN2 circuit board
operates normally as node of mLAN.
(Unconnected)
Word clock output from pin No.101 (WCKO)of mLAN-PH2 is
inputted. Used for audio signal mute circuit.
(Unconnected)
Word clock inputted to pin No.90 (WCKI)of mLAN-PH2 is
inputted. Used for audio signal mute circuit.
Connected to GND
(Unconnected)
(Unconnected)
Used to select response characteristic of PLL connected to
mLAN-PH2. (H level: Low jitter characteristic, L level:High-speed
response ) [Default on H level]
Used to control whether or not to bypass sampling frequency
converter of SRC board when SRC board is installed to CN7 of
MLN2 circuit board. (H level: Bypassing, L level: Not bypassing)
[Default on L level]

When clock to output audio signals from mLAN-PH2 is not
appropriate, outputs signal indicating that audio signals are not
subject to synchronization is output.
H level signal is inputted when using word clock output from
MLN2 circuit board as clock source of the main unit.
When selected as word clock master among mLAN units, signal
requesting to select the clock other then word clock output from
MLN2 circuit board as clock source to the main unit. (H level:
Word clock output from MLN2 circuit board is used as the
source, L level: Clock other than the word clock output from
MLN2 circuit board is used as the source)
Power supply (+3.3V)
Reset signal (L active) from the main unit with the MLN2 circuit
board installed is inputted.
When executing packet transmission in mLAN, signal to select
mLAN-NC1 or mLAN-PH2 for master operation is output. (H
level: mLAN-PH2 for master operation, L level: mLAN-NC1 for
master operation) [Default on L level]
Reset signal (L active) output by reset IC on MLN2 circuit board
is inputted.
GND
Power supply (+3.3V)
This terminal changes to H level when MLN2 circuit board
becomes route node of IEEE1349.
Connected to pin No.255 (CT) of mLAN-NC1
Connected to pin No.3 (IRXN) of mLAN-PH2
GND
Connected to pin No.229 (/IRERR) of mLAN-NC1
Connected to pin No.231 (/IRX) of mLAN-NC1
Connected to pin No.230 (/IRCV) of mLAN-NC1
Output terminal which is output enable (L active) for the flash
memory assigned to CE9 zone of mLAN-NC1

Output terminal which is write enable (L active) for the flash
memory assigned to CE9 zone of mLAN-NC1
(Unconnected)
(Unconnected)
Power supply (+3.3V)
Output terminal which is output enable (L active) for SRAM
assigned to CE9 zone of mLAN-NC1
(Unconnected)
Output terminal which is write enable (L active) for SRAM
assigned to CE9 zone of mLAN-NC1
(Unconnected)
Output terminal which is high byte enable (L active) for SRAM
assigned to CE9 zone of mLAN-NC1
Output terminal which is low byte enable (L active) for SRAM
assigned to CE9 zone of mLAN-NC1
Connected to pin No.130 (/CE9) of mLAN-NC1
GND
Connected to pin No.118 (/WRH) of mLAN-NC1
Connected to pin No.120 (/WRL) of mLAN-NC1
Terminal for loading data
Connected to pin No.123 (/RD) of mLAN-NC1
Connected to pin No.190 (CPU A0) of mLAN-NC1
Connected to pin No.187 (CPU A21) of mLAN-NC1
Power supply (+3.3V)
Connected to pin No.189 (CPU A20) of mLAN-NC1
Connected to pin No.164 (CPU A19) of mLAN-NC1
Chip select signal of mLAN-PH2 is output. Connected to pin
No.205 of mLAN-PH2.
(Unconnected)
Connected to pin No.156 (/CE4) of mLAN-NC1
(Unconnected)
Terminal for loading data
GND
Connected to pin No.145 (CPU D7) of mLAN-NC1
Connected to pin No.144 (CPU D6) of mLAN-NC1
(Unconnected)
(Unconnected)
Connected to pin No.143 (CPU D5) of mLAN-NC1
Connected to pin No.142 (CPU D4) of mLAN-NC1
Connected to pin No.140 (CPU D3) of mLAN-NC1
Power supply (+3.3V)
Connected to pin No.139 (CPU D2) of mLAN-NC1
Connected to pin No.138 (CPU D1) of mLAN-NC1
Connected to pin No.137 (CPU D0) of mLAN-NC1
GND
Any MIDI signal output by mLAN-NC1 is inputted. Connected to
pin No.58 (DA0[0]) of mLAN-NC1.
Connected to pin No.185 (CPU A22) of mLAN-NC1
Clock output from pin No.232 (ICLK) of mLAN-NC1 is inputted.
Bit clock (64Fs or 256Fs) from the main unit with MLN2 circuit
board installed is inputted.
Power supply (+3.3V)
Clock (128Fs or 64Fs) as a result of division of the clock inputted
to pin No.90 is output. Connected to pin No.87 (BCK128I) of
mLAN-PH2
Clock (64Fs) as a result of division of the clock inputted to pin
No.90 is output. Connected to pin No.88 (BCKI) of mLAN-PH2
Depending on operation condition, either lock signal of PLL
connected to mLAN-PH2 or lock signal detected by firmware of
mLAN-NC1 is output.
Connected to GND
Clock as a result of dividing ICLK (24.576MHz) output by mLAN-
NC1 by 512 is output. Connected to pin No.43 (WCKI) of mLAN-
NC1
Terminal to operate internal divider so that clock output from pin
No.92 and No.93 become 128Fs and 64Fs respectively when
clock inputted to pin No.90 is 256Fs. When set to H level, clock is
output from pins No.92 and No.93 without being divided. In such
case, 64Fs clock is inputted to pin No.90.
Lock signal of PLL connected to mLAN-PH2 is inputted.
Mute control signal of audio signal sent from the main unit with
MLN2 circuit board installed is output. (H level: Muting executed)
Mute control signal of audio signal sent to the main unit with
MLN2 circuit board installed is output. (H level: Muting executed)