i88X
18
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
LREQ
DVDD
SCLK
DVSS
CTL0
CTL1
DVDD
D0
D1
D2
D3
DVSS
D4
D5
D6
D7
DVDD
DVDD
TEST0
TEST1
DVSS
DVDD
DVSS
Purb
AGND
NC
NC
AVDD1
XEXT
XTAL
AGND
AVDD1
CPS
AGND
I
-
O
-
I/O
I/O
-
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
-
-
I
I
-
-
-
I
-
-
-
-
I/O
I/O
-
-
I
-
Link request
Digital power supply
49.152MHz link system clock
Digital ground
PHY-Link interface control signals
Digital power supply
PHY-Link interface data signals
Digital ground
PHY-Link interface data signals
Digital power supply
Test mode control terminals
Digital ground
Digital power supply
Digital ground
External capacitor connection terminal for
power-up reset
Analog ground
Non connection
Analog power supply 1
For crystal connections. Connection
terminals for quartz crystal oscillators.
Analog ground.
Analog power supply 1
A terminal for Cable Power Status detection
Analog ground
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AVDD1
TpBias1
TpBias0
TpB1n
TpB1p
TpA1n
TpA1p
TpB0n
TpB0p
TpA0n
TpA0p
AGND
AVDD2
DVSS
Disabled1
Disabled0
S200
LDSEL
DVDD
En_Accel
En_Multi
SR
DIRECT
DVSS
LinkOn
PC2
PC1
PC0
CMC
LPS
-
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
I
I
I
I
-
I
I
I
I
-
O
I
I
I
I
I
Analog power supply 1
A cable bias output terminal
A negative-phase-sequence I/O terminal
A positive-phase-sequence I/O terminal
A negative-phase-sequence I/O terminal
A positive-phase-sequence I/O terminal
A negative-phase-sequence I/O terminal
A positive-phase-sequence I/O terminal
A negative-phase-sequence I/O terminal
A positive-phase-sequence I/O terminal
Analog ground
Analog power supply 2
Digital ground
These pin define the initial value of the disable bits in the
PHY port status page after a hardware reset, and the
condition of the terminal of the level is reflected.
Phy Speed Control signal
Timing setting terminal for the PHY-Link interface
Digital power supply
This bit defines the initial value of the
Enab_accel bit after a hardware reset
This bit defines the initial value of the
Enab_multi bit after hardware reset
Suspend/Resume function control signal
Defines operation mode setting terminal for
the PHY-Link interface
Digital ground
Link-On signal output
Power Class
Configuration management capable setting terminal
Link power status
MD8408B (XZ762A00) PHY (Physical Layer)
MLN2: IC10
CS5351-KSR(X3782A00) MULTI-BIT AUDIO A/D CONVERTER
PIN
NAME I/O
FUNCTION
NO.
1
RST
I
Reset
The device enters a low power mode when low.
2
M/S
I
Master/Slave Mode
Selects operation as either clock master or slave.
3
LRCK
I/O
Left/Right Clock
Determines which channel, Left or Right, is currently active on the serial audio data line.
4
SCLK
I/O
Serial Clock
Serial clock for the serial audio interface.
5
MCLK
I
Master Clock
Clock source for the delta-sigma modulator and digital filters.
6
VD
I
Digital Power
Positive power supply for the digital section.
7
GND
I
Ground
Ground reference. Must be connected to analog ground.
8
VL
I
Logic Power
Positive power for the digital input/output.
9
SDOUT
O
Serial Audio Data Output
Output for two's complement serial audio data.
10
MDIV
I
MCLK Divider
Enables a master clock divide by two function.
11
HPF
I
High Pass Filter Enable
Enables the Digital High-Pass Filter.
12
I
2
S/LJ
I
Serial Audio Interface Format Select
Selects either the left-justified or I
2
S format for the SAI.
PIN
NAME I/O
FUNCTION
NO.
13
M0
I
Mode Selection
14
M1
Determines the operational mode of the device.
15 OVFL
O
Overflow
Detects an overflow condition on both left and right channels.
16
AINR
I
Analog Input
17 VQ1
I/O
Quiescent
Voltage
18
GND
I
Ground
Ground reference. Must be connected to analog ground.
19
VA
I
Analog Power
20
VQ2
Filter connection for the internal quiescent reference voltage.
21 AINL
The full scale analog input level is specified
in the Analog Characteristics specification table.
22
VQ3
Positive power supply for the analog section.
23
REF_GND
I
Reference Ground
Ground reference for the internal sampling circuits.
24
FILT+ O
Positive
Voltage
Reference
Positive reference voltage for the internal sampling circuits.
DM: IC12, IC13, IC14
